Patents by Inventor Li Feng

Li Feng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190148389
    Abstract: A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.
    Type: Application
    Filed: June 29, 2018
    Publication date: May 16, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Han Lin, Te-Hsin Chiu, Wei-Cheng Wu, Li-Feng Teng, Chien-Hung Chang
  • Patent number: 10283512
    Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate. A second dielectric layer is disposed between the floating gate and the control gate, having one of a silicon nitride layer, a silicon oxide layer and multilayers thereof. A third dielectric layer is disposed between the second dielectric layer and the control gate, and includes a dielectric material having a dielectric constant higher than silicon nitride.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei Cheng Wu, Li-Feng Teng
  • Publication number: 20190097028
    Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate and having one of a silicon oxide layer, a silicon nitride layer and multilayers of silicon oxide and silicon nitride, and an erase gate and a select gate. The erase gate and the select gate include a stack of a bottom polysilicon layer and an upper metal layer.
    Type: Application
    Filed: November 28, 2018
    Publication date: March 28, 2019
    Inventors: Wei Cheng WU, Li-Feng TENG
  • Publication number: 20190064296
    Abstract: Exemplary method, system and computer-accessible medium can be provided which facilitates an acquisition of radial data, which can be continuous, with an exemplary golden-angle procedure and reconstruction with arbitrary temporal resolution at arbitrary time points. According to such exemplary embodiment, such procedure can be performed with a combination of compressed sensing and parallel imaging to offer a significant improvement, for example in the reconstruction of highly undersampled data. It is also possible to provide an exemplary procedure for highly-accelerated dynamic magnetic resonance imaging using Golden-Angle radial sampling and multicoil compressed sensing reconstruction, called Golden-angle Radial Sparse Parallel MRI (GRASP).
    Type: Application
    Filed: March 19, 2018
    Publication date: February 28, 2019
    Inventors: Ricardo Otazo, Li Feng, Tobias Block, Hersh Chandarana, Leon Axel, Daniel K. Sodickson
  • Patent number: 10164074
    Abstract: A semiconductor device includes a semiconductor substrate, a gate dielectric layer, a gate electrode and source and drain regions. The gate dielectric layer extends into a first trench in the semiconductor substrate. The gate electrode is over the gate dielectric layer and is at least partially embedded in the first trench in the semiconductor substrate. The source and drain regions are in the semiconductor substrate and proximate the first trench in the semiconductor substrate.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Cheng Wu, Li-Feng Teng, Alexander Kalnitsky
  • Patent number: 10143011
    Abstract: The present invention provides a method for processing channel access and an apparatus thereof. The method includes: receiving a fallback to physical random access channel (PRACH) indication sent by a base station; and initiating access on a common enhanced dedicated channel (E-DCH). In the present invention, a fallback to PRACH indication is not executed, so as to prevent a user terminal from being in a DRX off state when a base station sends downlink data to the UE, thereby preventing the base station from delaying sending the downlink data to the UE.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: November 27, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Xiaoxiao Zheng, Xudong Yang, Li Feng
  • Patent number: 10112240
    Abstract: A milling cutter is configured to process an edge of a workpiece to a required profile. The required profile includes a first portion and a second portion coupled to the first portion. The milling cutter includes a shank having a central axis, at least one first cutting edge, and at least one second cutting edge. The first cutting edge is configured to rotate around the central axis of the shank along a first rotation path to process the first portion of the predetermined profile, and the second cutting edge is configured to rotate around the central axis of the shank along a second rotation path to process the second portion of the predetermined profile. The first rotation path is different from, and connected to the second rotation path.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: October 30, 2018
    Assignee: JI ZHUN PRECISION INDUSTRY (HUI ZHOU) CO., LT
    Inventors: Jun-Qi Li, Yi-Min Jiang, Long Xu, Li-Feng Zhan
  • Patent number: 10034853
    Abstract: The present invention discloses a PPAR ?/? dual agonist and its application. The PPAR ?/? dual agonist comprises an effective amount of the compounds represented by formula I or/and its pharmaceutically acceptable derivative. Wherein. R1 is selected from alkoxyl or ester group; R2 is selected from hydroxyl or ester group. The PPAR ?/? dual agonist according to the present invention can be used for preparing drugs and functional foods for preventing or/and treating metabolic syndrome, especially glucose or/and lipid disorders, with extensive and bright prospects of application.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: July 31, 2018
    Assignee: Shanghai University of Traditional Chinese Medicine
    Inventors: Fujiang Guo, Cheng Huang, Li Feng, Yiming Li
  • Patent number: 10007736
    Abstract: A processor of an electronic device can implement methods that facilitate navigating a webpage. The methods may include: receiving (602) data for a target webpage and storing (604) the target webpage data to a processor readable storage medium of the electronic device and determining (606) whether the target webpage's uniform resource locator (URL) was selected from a search results page generated by a search engine executing a search string. If the target webpage's URL was selected from a search results page, performing (650) a particular action. The particular action can include steps of: searching (851) the stored target webpage data for one or more instances of one or more parts of the search string, prioritizing (852) the one or more instances, and resizing (858) one or more parts of the target webpage having the one or more instances with the highest priority.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: June 26, 2018
    Assignee: Google Technology Holdings LLC
    Inventors: Li-Feng Liang, Kun Zhao
  • Patent number: 10001930
    Abstract: A method for implementing a packet I/O engine on a programmable computing platform is provided, where the engine performs I/O functions for plural threads generated by a plurality of user applications. In the method, the platform is configured such that only one thread is permitted to initialize and configure the resources. Furthermore, I/O-device queues each for buffering packets either transmitted to or received from an individual external I/O device are set up. For a plurality of unsafe I/O-device queues determined, among the I/O-device queues, to be multi-thread unsafe, a plurality of multi-producer, multi-consumer software queues for buffering packets delivered between the plurality of the unsafe I/O-device queues and the plurality of user applications is set up.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: June 19, 2018
    Assignee: Macau University of Science and Technology
    Inventors: Li Feng, Liang Zhou, Zhijun Xu, Yujun Zhang
  • Publication number: 20180155626
    Abstract: The present invention discloses a substance vehicle of pyrolysis reactor to apply for loading the substances of pyrolysis reactor. The substance vehicle includes a vehicle body, at least two movable doors and at least two fixed units. The vehicle body is used to accommodate the pyrolysis substances, and the movable door is movably disposed at the bottom of the vehicle body. When the fixed units are changed from the first position to the second position, a part of the fixed unit will disengage from the bottom of the movable door, such that the movable doors are opened by gravity and the pyrolysis substances are dropped.
    Type: Application
    Filed: February 1, 2018
    Publication date: June 7, 2018
    Inventor: Li-Feng Cheng
  • Publication number: 20180151707
    Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate and having one of a silicon oxide layer, a silicon nitride layer and multilayers of silicon oxide and silicon nitride, and an erase gate and a select gate. The erase gate and the select gate include a stack of a bottom polysilicon layer and an upper metal layer.
    Type: Application
    Filed: July 12, 2017
    Publication date: May 31, 2018
    Inventors: Wei Cheng WU, Li-Feng TENG
  • Publication number: 20180151582
    Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate. A second dielectric layer is disposed between the floating gate and the control gate, having one of a silicon nitride layer, a silicon oxide layer and multilayers thereof. A third dielectric layer is disposed between the second dielectric layer and the control gate, and includes a dielectric material having a dielectric constant higher than silicon nitride.
    Type: Application
    Filed: May 2, 2017
    Publication date: May 31, 2018
    Inventors: Wei Cheng WU, Li-Feng TENG
  • Publication number: 20180151581
    Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.
    Type: Application
    Filed: February 9, 2017
    Publication date: May 31, 2018
    Inventors: Wei Cheng WU, Li-Feng TENG
  • Publication number: 20180151580
    Abstract: A semiconductor device includes a semiconductor substrate, a gate dielectric layer, a gate electrode and source and drain regions. The gate dielectric layer extends into a first trench in the semiconductor substrate. The gate electrode is over the gate dielectric layer and is at least partially embedded in the first trench in the semiconductor substrate. The source and drain regions are in the semiconductor substrate and proximate the first trench in the semiconductor substrate.
    Type: Application
    Filed: May 22, 2017
    Publication date: May 31, 2018
    Inventors: Wei-Cheng WU, Li-Feng TENG, Alexander KALNITSKY
  • Patent number: 9961002
    Abstract: Compute-intensive packet processing (CIPP) in a computer system comprising a programmable computing platform is accelerated by using a packet I/O engine, implemented on the platform, to perform packet I/O functions, where the packet I/O engine is configured to achieve direct access to a network interface card (NIC) from a user application. For a Linux-based computer system, standard I/O mechanisms of Linux are bypassed and only the packet I/O engine is used in performing the I/O functions. Furthermore, the computer system is configured to: process a batch of packets, instead of packet by packet, in every function call; and when moving a packet between a buffer of an individual user application and a queue of the packet I/O engine, copy a packet descriptor of the packet instead the entire packet. In addition, workflows across different working threads are balanced and parallelism is exploited to fully utilize resources of the platform.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: May 1, 2018
    Assignee: Macau University of Science and Technology
    Inventors: Li Feng, Liang Zhou, Zhijun Xu, Yujun Zhang
  • Patent number: 9921285
    Abstract: Exemplary method, system and computer-accessible medium can be provided which facilitates an acquisition of radial data, which can be continuous, with an exemplary golden-angle procedure and reconstruction with arbitrary temporal resolution at arbitrary time points. According to such exemplary embodiment, such procedure can be performed with a combination of compressed sensing and parallel imaging to offer a significant improvement, for example in the reconstruction of highly undersampled data. It is also possible to provide an exemplary procedure for highly-accelerated dynamic magnetic resonance imaging using Golden-Angle radial sampling and multicoil compressed sensing reconstruction, called Golden-angle Radial Sparse Parallel MRI (GRASP).
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: March 20, 2018
    Assignee: New York University
    Inventors: Ricardo Otazo, Li Feng, Tobias Block, Hersh Chandarana, Leon Axel, Daniel K. Sodickson
  • Patent number: 9906010
    Abstract: A driving device is configured to drive a power semiconductor switch module based on a main control signal. The driving device includes a voltage-modulating unit and a driving module. When the voltage-modulating unit receives a protection signal, the voltage-modulating unit generates a turn-off pulse signal based on the protection signal. Moreover, the driving module is configured to turn off the power semiconductor switch module based on the turn-off pulse signal. Also disclosed herein is a driving method.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: February 27, 2018
    Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.
    Inventors: Tao Jiang, Li-Feng Qiao, Jian-Gang Huang, Yang-Yang Tao, Hong-Jian Gan
  • Patent number: 9900768
    Abstract: Embodiments of the present invention provide a method and a device for synchronizing an uplink ciphering parameter in unacknowledged mode. The method for synchronizing an uplink ciphering parameter in unacknowledged mode includes: sending an indication message to a terminal when detecting that an unrecoverable error occurs in an uplink packet or that the uplink packet is invalid, where the indication message is used to instruct the terminal to initialize an uplink ciphering parameter; receiving a response message sent by the terminal; and initializing the uplink ciphering parameter according to an initial value of the ciphering parameter. The embodiments of the present invention solve a service defect, namely, a break of the communication link caused by synchronization of an uplink ciphering parameter between the terminal and the radio network controller in unacknowledged mode, and shorten the time of synchronizing the uplink ciphering parameter without interrupting the service.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: February 20, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Xiaoxiao Zheng, Yinghong Yang, Li Feng, Xiaoying Xu, Zhufen Fu, Lunfeng Yu, Yafei Sun
  • Patent number: 9887534
    Abstract: A short-circuit detecting device includes a coil and a processing circuit. The coil is configured to detect a variation of magnetic flux intensity generated by a current variation of a current flowing through a power semiconductor switch and to generate an induced electromotive force based on the variation of magnetic flux intensity. When the current variation rate of said current is greater than a predetermined value, the processing circuit is configured to generate a short-circuit signal based on the induced electromotive force so as to turn off the power semiconductor switch based on the short-circuit signal.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: February 6, 2018
    Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.
    Inventors: Ming Wang, Jian-Ping Ying, Jian-Gang Huang, Li-Feng Qiao, Tao Jiang