Patents by Inventor Liang Chu
Liang Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12292160Abstract: An automatic dropping lubricating device comprises a tank body, a stirring mechanism, a filter mechanism and an intermittent mechanism, a drive motor is fixedly connected to the middle of the right side wall of the tank body, the stirring mechanism is rotationally connected to the middle of an inner cavity of the tank body, the filter mechanism is fixedly connected to the middle of a charging pipe, and the intermittent mechanism is arranged on the right side of the bottom of the tank body. The invention drives a telescopic rod to rotate so that the telescopic rod props against a trigger slider for sliding and the trigger slider drives a movable plate to slide; when the movable plate slides, a connecting pipe slides in a second chute, and finally the connecting pipe is connected to a dropping port while a dropping pipe is connected to the connecting pipe.Type: GrantFiled: August 10, 2023Date of Patent: May 6, 2025Assignee: HUANENG JIAXIANG POWER GEBERATION CO., LTD.Inventors: Tao Lin, Liang Chu, Qimeng Zhang
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Patent number: 12268098Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.Type: GrantFiled: December 4, 2023Date of Patent: April 1, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chung-Liang Chu, Jian-Cheng Chen, Yu-Ping Wang, Yu-Ruei Chen
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Patent number: 12237323Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.Type: GrantFiled: January 5, 2024Date of Patent: February 25, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Fu Hsu, Ta-Yuan Kung, Chen-Liang Chu, Chih-Chung Tsai
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Patent number: 12211935Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate of a first conductivity; a first region of the first conductivity formed in the substrate; a second region of the first conductivity formed in the first region, wherein the second region has a higher doping density than the first region; a source region of a second conductivity formed in the second region; a drain region of the second conductivity formed in the substrate; a pickup region of the first conductivity formed in the second region and adjacent to the source region; and a resist protective oxide (RPO) layer formed on a top surface of the second region. An associated fabricating method is also disclosed.Type: GrantFiled: November 20, 2022Date of Patent: January 28, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chen-Liang Chu, Ta-Yuan Kung, Ker-Hsiao Huo, Yi-Huan Chen
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Patent number: 12176407Abstract: A method to form a transistor device with a recessed gate structure is provided. In one embodiment, a gate structure is formed overlying a device region and an isolation structure. The gate structure separates a device doping well along a first direction with a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A pair of source/drain regions in is formed the device region on opposite sides of the gate structure. A sidewall spacer is formed extending along sidewalls of the gate structure, where a top surface of the sidewall spacer is substantially flush with the top surface of the gate structure. A resistive protection layer is then formed on the sidewall spacer and covering the pair of recess regions.Type: GrantFiled: July 27, 2022Date of Patent: December 24, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Liang Chu, Chien-Chih Chou, Chih-Chang Cheng, Yi-Huan Chen, Kong-Beng Thei, Ming-Ta Lei, Ruey-Hsin Liu, Ta-Yuan Kung
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Patent number: 12145688Abstract: A bicycle brake lever includes a main body, a brake assembly, and a valve. The main body includes a casing and a cover mounted on the casing. The casing has a storage chamber and a hydraulic chamber. The brake assembly includes a lever, a link, and a piston. The lever is pivotally disposed on the casing, the link connects the lever and the piston, the link is disposed through the cover, the piston is movably located in the hydraulic chamber and has an inner channel in fluid communication with the storage chamber. The valve is movably disposed on the casing. The valve is partially located in the hydraulic chamber. When the piston is moved from an initial position to a sealed position, the valve blocks the inner channel of the piston, such that the hydraulic chamber is not in fluid communication with the storage chamber.Type: GrantFiled: June 16, 2022Date of Patent: November 19, 2024Assignee: TEKTRO TECHNOLOGY CORPORATIONInventor: En-Liang Chu
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Publication number: 20240379845Abstract: A medium voltage transistor of a level shifter circuit may include a p-well region in a substrate. Moreover, the medium voltage transistor may include an n-type lightly-doped source/drain (NLDD) region in which an N+ source/drain region of the medium voltage transistor is included. The light doping in the NLDD region enables a threshold voltage (Vi) to be reduced while enabling medium voltage operation at the N+ source/drain region. To reduce the amount of current leakage in the medium voltage transistor due to the light doping in the NLDD region, a buffer layer may be included over and/or on a portion of the NLDD region under a gate structure of the medium voltage transistor. The NLDD region and the thermal region of the medium voltage transistor enables the threshold voltage of the medium voltage transistor while maintaining the same current leakage performance or reducing current leakage in the medium voltage transistor.Type: ApplicationFiled: May 11, 2023Publication date: November 14, 2024Inventors: Chen-Liang CHU, Hsin-Chih CHIANG, Ruey-Hsin LIU, Ta-Yuan KUNG, Ta-Chuan LIAO, Chih-Wen YAO, Ming-Ta LEI
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Publication number: 20240379789Abstract: A method to form a transistor device with a recessed gate structure is provided. In one embodiment, a gate structure is formed overlying a device region and an isolation structure. The gate structure separates a device doping well along a first direction with a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A pair of source/drain regions in is formed the device region on opposite sides of the gate structure. A sidewall spacer is formed extending along sidewalls of the gate structure, where a top surface of the sidewall spacer is substantially flush with the top surface of the gate structure. A resistive protection layer is then formed on the sidewall spacer and covering the pair of recess regions.Type: ApplicationFiled: July 23, 2024Publication date: November 14, 2024Inventors: Chen-Liang Chu, Chien-Chih Chou, Chih-Chang Cheng, Yi-Huan Chen, Kong-Beng Thei, Ming-Ta Lei, Ruey-Hsin Liu, Ta-Yuan Kung
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Publication number: 20240379791Abstract: A semiconductor structure includes semiconductor structure includes a metal gate structure, a plurality of dielectric pillars disposed in the metal gate structure, a source/drain structure disposed at tow side of the metal gate structure, and at least a first connecting structure disposed over one of the dielectric pillars and coupled to the metal gate structure. The first connecting structure overlaps the one of the dielectric pillars entirely from a top view. An area of the first connecting structure is greater than an area of the one of the dielectric pillars from the top view.Type: ApplicationFiled: May 10, 2023Publication date: November 14, 2024Inventors: TA-CHUAN LIAO, CHEN-LIANG CHU, HSIN-CHIH CHIANG, MING-TA LEI, TA-YUAN KUNG
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Publication number: 20240357943Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.Type: ApplicationFiled: June 30, 2024Publication date: October 24, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chiu-Jung Chiu, Ya-Sheng Feng, I-Ming Tseng, Yi-An Shih, Yu-Chun Chen, Yi-Hui Lee, Chung-Liang Chu, Hsiu-Hao Hu
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Patent number: 12087666Abstract: A semiconductor device includes a substrate, an isolation structure, a first gate structure, a second gate structure, a first slot contact structure, a first gate contact structure, and a second gate contact structure. The substrate includes a first active region and a second active region elongated in a first direction respectively. The first gate structure, the second gate structure, and the first slot contact structure are continuously elongated in a second direction respectively. The first gate contact structure and the second gate contact structure are disposed at two opposite sides of the first slot contact structure in the first direction respectively.Type: GrantFiled: December 7, 2022Date of Patent: September 10, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chung-Liang Chu, Yu-Ruei Chen
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Patent number: 12063871Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.Type: GrantFiled: August 4, 2023Date of Patent: August 13, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chiu-Jung Chiu, Ya-Sheng Feng, I-Ming Tseng, Yi-An Shih, Yu-Chun Chen, Yi-Hui Lee, Chung-Liang Chu, Hsiu-Hao Hu
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Publication number: 20240258373Abstract: An integrated chip including a first source/drain region and a second source/drain region in a semiconductor substrate and laterally spaced apart along a top surface of the substrate. A gate dielectric layer is over the substrate and extends laterally between the first source/drain region and the second source/drain region. A thickness of the gate dielectric layer along a first sidewall of the gate dielectric layer is less than an average thickness of the gate dielectric layer. A trench isolation layer extends along gate dielectric layer. A first sidewall of the trench isolation layer extends along the first sidewall of the gate dielectric layer. A gate layer is directly over the gate dielectric layer and between the first source/drain region and the second source/drain region. A first sidewall of the gate layer is directly over the gate dielectric layer and laterally setback from the first sidewall of the gate dielectric layer.Type: ApplicationFiled: February 1, 2023Publication date: August 1, 2024Inventors: Ta-Yuan Kung, Chen-Liang Chu, Chih-Wen Albert Yao, Fei-Yun Chen, Ming-Ta Lei, Ruey-Hsin Liu, Yu-Chang Jong
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Publication number: 20240240089Abstract: Provided are a standing coke-making furnace, a coke-making system and a method thereof.Type: ApplicationFiled: June 20, 2023Publication date: July 18, 2024Inventors: Chenglong Yang, Yang Li, Hanchen Zhao, Ming Cai, Chenguang Jia, Mingyu Yao, Jun Zhang, Liang Chu, Yi Cui, Hongqing Zhang, Jie Guo, Zaisong Yu, Faguang Liang
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Publication number: 20240221561Abstract: A flexible display module and an electronic device are provided in the present application; when a main display screen of the flexible display module is in a flattened state, a supporting member extends out of a supporting component, and the main display screen is located on the supporting component and the supporting member; when the main display screen is in a bent state, at least part of the supporting member is retracted into the supporting component. This way, displacement generated when a flexible display panel is bent is compensated by telescopic movement of a telescopic component, so as to alleviate a problem of gaps generated in a frame when an existing folding display device is bent.Type: ApplicationFiled: April 25, 2022Publication date: July 4, 2024Applicant: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.Inventor: Liang Chu
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Publication number: 20240186408Abstract: Transistors with improved saturation drain current and methods for making such transistors are disclosed. The gate is formed in the shape of a longitudinal trench and a plurality of lateral trenches below the longitudinal trench. The resulting dual-recess structure increases the surface area of the gate, which permits additional charge carriers and increases the saturation drain current of the transistor. Such transistors can be useful in high voltage and medium voltage applications such as in display driver integrated circuits.Type: ApplicationFiled: January 5, 2023Publication date: June 6, 2024Inventors: Chen-Liang Chu, Chien-Chih Chou, Ta-Yuan Kung, Chun-Hsun Lee, Chih-Wen Yao, Yi-Huan Chen, Ming-Ta Lei
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Patent number: 11999437Abstract: A bicycle hydraulic assembly includes a casing, a first piston, and a second piston. The casing has a hydraulic chamber, an inlet channel, and an outlet channel connected to the hydraulic chamber. The first piston is located in the hydraulic chamber. The second piston is sleeved on the first piston. The second piston has a first end portion and a second end portion opposite to each other. The first end portion is wider than the second end portion located farther away from the inlet channel than the first end portion. When the first piston is moved a distance smaller than a threshold distance, the first piston is moved relative to the second piston while the second piston is stationary relative to the casing. When the first piston is moved a distance greater than the threshold distance, the first piston forces the second piston to move relative to the casing.Type: GrantFiled: September 3, 2021Date of Patent: June 4, 2024Assignee: TEKTRO TECHNOLOGY CORPORATIONInventor: En-Liang Chu
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Publication number: 20240153943Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.Type: ApplicationFiled: January 5, 2024Publication date: May 9, 2024Inventors: Sheng-Fu Hsu, Ta-Yuan Kung, Chen-Liang Chu, Chih-Chung Tsai
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Publication number: 20240107895Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.Type: ApplicationFiled: December 4, 2023Publication date: March 28, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chung-Liang Chu, Jian-Cheng Chen, Yu-Ping Wang, Yu-Ruei Chen
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Patent number: 11916060Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.Type: GrantFiled: June 21, 2022Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Fu Hsu, Ta-Yuan Kung, Chen-Liang Chu, Chih-Chung Tsai