Abstract: A fin transistor structure is provided. The fin transistor structure includes a first substrate. An insulation layer is disposed on the first substrate. A plurality of fin structures are disposed on the insulation layer. A supporting dielectric layer fixes the fin structures at the fin structures at waist parts thereof. A gate structure layer is disposed on the supporting dielectric layer and covers a portion of the fin structures.

Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, wherein the ring of MTJ region comprises a first MTJ, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, each of the metal interconnect patterns includes a first metal interconnection connected to the first MTJ directly.

Abstract: A semiconductor device includes a substrate, an isolation structure, a first gate structure, a second gate structure, a first slot contact structure, a first gate contact structure, and a second gate contact structure. The substrate includes a first active region and a second active region elongated in a first direction respectively. The first gate structure, the second gate structure, and the first slot contact structure are continuously elongated in a second direction respectively. The first gate contact structure and the second gate contact structure are disposed at two opposite sides of the first slot contact structure in the first direction respectively.

Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the ring of MTJ region comprises an octagon and the ring of MTJ region includes a first MTJ region and a second MTJ region extending along a first direction, a third MTJ region and a fourth MTJ region extending along a second direction, a fifth MTJ region and a sixth MTJ region extending along a third direction, and a seventh MTJ region and an eighth MTJ region extending along a fourth direction.

Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate, a gate, a first doped region and a second doped region. The gate is over the substrate. The first doped region and the second doped region are in the substrate. The first doped region and the second doped region are of a same conductivity type and separated by the gate. The length of the first doped region is greater than a length of the second doped region in a direction substantially perpendicular to a channel length defined between the first doped region and the second doped region.

Abstract: A semiconductor device includes a substrate, an isolation structure, a first gate structure, a second gate structure, a first slot contact structure, a first gate contact structure, and a second gate contact structure. The substrate includes a first active region and a second active region elongated in a first direction respectively. The first gate structure, the second gate structure, and the first slot contact structure are elongated in a second direction respectively. The first gate contact structure and the second gate contact structure are disposed at two opposite sides of the first slot contact structure in the first direction respectively and disposed between the first active region and the second active region in the second direction. A length of the first gate contact structure and a length of the second gate contact structure in the second direction are less than a length of the isolation structure in the second direction.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate of a first conductivity; a first region of the first conductivity formed in the substrate; a second region of the first conductivity formed in the first region, wherein the second region has a higher doping density than the first region; a source region of a second conductivity formed in the second region; a drain region of the second conductivity formed in the substrate; a pickup region of the first conductivity formed in the second region and adjacent to the source region; and a resist protective oxide (RPO) layer formed on a top surface of the second region. An associated fabricating method is also disclosed.

Abstract: A dummy cell arrangement in a semiconductor device includes a substrate with a dummy region, unit dummy cells arranged in rows and columns in the dummy region, and flexible extended dummy cells arranged in rows and columns filling up remaining dummy region. The unit dummy cell includes exactly one base dummy cell and exactly two fixed dummy cells at opposite sides of the base dummy cell in row direction or in column direction and the flexible extended dummy cell includes at least two base dummy units and a plurality of flexible dummy units at two opposite sides of the two base dummy units in row direction or in column direction. The base dummy cell consists of at least one fin, at least one gate and at least one contact, while the flexible dummy cell consists of one gate and one contact without any fin.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate of a first conductivity; a first region of the first conductivity formed in the substrate; a second region of the first conductivity formed in the first region, wherein the second region has a higher doping density than the first region; a source region of a second conductivity formed in the second region; a drain region of the second conductivity formed in the substrate; a pickup region of the first conductivity formed in the second region and adjacent to the source region; and a resist protective oxide (RPO) layer formed on a top surface of the second region. An associated fabricating method is also disclosed.

Abstract: The present invention provides a method for preparing a reconstituted apolipoprotein B lipoparticle and the method comprises steps of (a) dissolving an apolipoprotein B and a lipid in a first buffer containing 2 M to 8 M urea and 1 wt % to 15 wt % amphiphilic compounds to form a mixture; and (b) dialyzing the mixture against a second buffer containing 0 M to 2M urea and 0 wt % to 0.5 wt % amphiphilic compounds for 1 to several times for lowering concentrations of the urea and the amphiphilic compounds in the mixture. The present invention further provides an apolipoprotein B lipoparticle and a use for the production of an apolipoprotein B lipoparticle used for delivering a hydrophobic substance.

Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate, a gate, a first doped region and a second doped region. The gate is over the substrate. The first doped region and the second doped region are in the substrate. The first doped region and the second doped region are of a same conductivity type and separated by the gate. The length of the first doped region is greater than a length of the second doped region in a direction substantially perpendicular to a channel length defined between the first doped region and the second doped region.

Abstract: A semiconductor device includes a semiconductor substrate, a gate dielectric, a gate electrode, a pair of source/drain regions, a pair of first well regions, a second well region, a pair of contact regions and a pair of third well regions. The gate dielectric is disposed in the semiconductor substrate having a concave profile that defines an upper boundary lower than an upper surface of the semiconductor substrate. The gate electrode is disposed over the gate dielectric. The pair of source/drain regions are disposed on opposing sides of the gate dielectric. The pair of first well regions are disposed under the pair of source/drain regions. The second well region is disposed between the pair of first well regions. The pair of contact regions are disposed on opposing sides of the pair of source/drain regions. The pair of third well regions are disposed under the pair of contact regions.

Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate, a gate, a first doped region and a second doped region. The gate is over the substrate. The first doped region and the second doped region are in the substrate. The first doped region and the second doped region are of a same conductivity type and separated by the gate. The length of the first doped region is greater than a length of the second doped region in a direction substantially perpendicular to a channel length defined between the first doped region and the second doped region.

Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes: a first magnetic tunneling junction (MTJ) pattern on a substrate; a second MTJ pattern adjacent to the first MTJ pattern; and a first metal interconnection pattern between the first MTJ pattern and the second MTJ pattern, wherein the first MTJ pattern, the first metal interconnection pattern, and the second MTJ pattern comprise a staggered arrangement.

Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes: a first magnetic tunneling junction (MTJ) pattern on a substrate; a second MTJ pattern adjacent to the first MTJ pattern; and a first metal interconnection pattern between the first MTJ pattern and the second MTJ pattern, wherein the first MTJ pattern, the first metal interconnection pattern, and the second MTJ pattern comprise a staggered arrangement.

Abstract: A semiconductor device includes a semiconductor substrate, a gate dielectric, a gate electrode and a pair of source/drain regions. The gate dielectric is disposed in the semiconductor substrate having a concave profile that defines an upper boundary lower than an upper surface of the semiconductor substrate. The gate electrode is disposed over the gate dielectric. The pair of source/drain regions are disposed on opposing sides of the gate dielectric.

Abstract: Some embodiments of the present disclosure relate to a method of forming a transistor. The method includes forming a gate dielectric over a substrate and forming a gate over the gate dielectric. The gate includes polysilicon extending between a first outermost sidewall and a second outermost sidewall of the gate. A mask is formed over the gate. The mask exposes a first gate region extending to the first outermost sidewall and covers a second gate region extending between the first gate region and the second outermost sidewall. Dopants are selectively implanted into the first gate region according to the mask. Source and drain regions are formed within the substrate. The source region and the drain region are asymmetric with respect to an interface of the first gate region and the second gate region and extend to substantially equal distances past the first and second outermost sidewalls of the gate, respectively.

Abstract: The present invention provides a method to convert the intrinsic sugar of a juice into indigestible oligosaccharides (such as, low-polymerization fructose and sorbitol). The present method comprises using a Zymomonas mobilis biomass and fructosyltransferase as well as pressure treatment. Taking advantage of the present method, the drawbacks of drinking juices, such as too many sugar and calorie intake can be obviated, and thereby the present invention can offer healthier option to the consumers.

Abstract: A method of fabricating an integrated circuit includes the following steps. A first reticle is used to form a first pattern, wherein the first pattern includes a first feature and a first jog part protruding from and orthogonal to the first feature. A second reticle is used to form a second pattern, wherein the second pattern includes a second feature, and the first feature is between the second feature and the first jog part. A third reticle is used to form a third pattern, wherein the third pattern includes a third-one feature overlapping the first jog part and a third-two feature overlapping the second feature.

Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, wherein the ring of MTJ region comprises a first MTJ, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, each of the metal interconnect patterns includes a first metal interconnection connected to the first MTJ directly.