Patents by Inventor Liang Chu

Liang Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200295148
    Abstract: A semiconductor device includes a semiconductor substrate, a gate dielectric, a gate electrode, a pair of source/drain regions, a pair of first well regions, a second well region, a pair of contact regions and a pair of third well regions. The gate dielectric is disposed in the semiconductor substrate having a concave profile that defines an upper boundary lower than an upper surface of the semiconductor substrate. The gate electrode is disposed over the gate dielectric. The pair of source/drain regions are disposed on opposing sides of the gate dielectric. The pair of first well regions are disposed under the pair of source/drain regions. The second well region is disposed between the pair of first well regions. The pair of contact regions are disposed on opposing sides of the pair of source/drain regions. The pair of third well regions are disposed under the pair of contact regions.
    Type: Application
    Filed: June 1, 2020
    Publication date: September 17, 2020
    Inventors: TA-YUAN KUNG, RUEY-HSIN LIU, CHEN-LIANG CHU, CHIH-WEN YAO, MING-TA LEI
  • Publication number: 20200266295
    Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate, a gate, a first doped region and a second doped region. The gate is over the substrate. The first doped region and the second doped region are in the substrate. The first doped region and the second doped region are of a same conductivity type and separated by the gate. The length of the first doped region is greater than a length of the second doped region in a direction substantially perpendicular to a channel length defined between the first doped region and the second doped region.
    Type: Application
    Filed: May 8, 2020
    Publication date: August 20, 2020
    Inventors: Ker-Hsiao HUO, Kong-Beng THEI, Chien-Chih CHOU, Yi-Min CHEN, Chen-Liang CHU
  • Patent number: 10714466
    Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes: a first magnetic tunneling junction (MTJ) pattern on a substrate; a second MTJ pattern adjacent to the first MTJ pattern; and a first metal interconnection pattern between the first MTJ pattern and the second MTJ pattern, wherein the first MTJ pattern, the first metal interconnection pattern, and the second MTJ pattern comprise a staggered arrangement.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: July 14, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Liang Chu, Chih-Hsien Tang, Yu-Ruei Chen, Ya-Huei Tsai, Rai-Min Huang, Chueh-Fei Tai
  • Publication number: 20200212030
    Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes: a first magnetic tunneling junction (MTJ) pattern on a substrate; a second MTJ pattern adjacent to the first MTJ pattern; and a first metal interconnection pattern between the first MTJ pattern and the second MTJ pattern, wherein the first MTJ pattern, the first metal interconnection pattern, and the second MTJ pattern comprise a staggered arrangement.
    Type: Application
    Filed: January 23, 2019
    Publication date: July 2, 2020
    Inventors: Chung-Liang Chu, Chih-Hsien Tang, Yu-Ruei Chen, Ya-Huei Tsai, Rai-Min Huang, Chueh-Fei Tai
  • Patent number: 10686047
    Abstract: A semiconductor device includes a semiconductor substrate, a gate dielectric, a gate electrode and a pair of source/drain regions. The gate dielectric is disposed in the semiconductor substrate having a concave profile that defines an upper boundary lower than an upper surface of the semiconductor substrate. The gate electrode is disposed over the gate dielectric. The pair of source/drain regions are disposed on opposing sides of the gate dielectric.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ta-Yuan Kung, Ruey-Hsin Liu, Chen-Liang Chu, Chih-Wen Yao, Ming-Ta Lei
  • Patent number: 10680019
    Abstract: Some embodiments of the present disclosure relate to a method of forming a transistor. The method includes forming a gate dielectric over a substrate and forming a gate over the gate dielectric. The gate includes polysilicon extending between a first outermost sidewall and a second outermost sidewall of the gate. A mask is formed over the gate. The mask exposes a first gate region extending to the first outermost sidewall and covers a second gate region extending between the first gate region and the second outermost sidewall. Dopants are selectively implanted into the first gate region according to the mask. Source and drain regions are formed within the substrate. The source region and the drain region are asymmetric with respect to an interface of the first gate region and the second gate region and extend to substantially equal distances past the first and second outermost sidewalls of the gate, respectively.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Liang Chu, Chih-Wen Albert Yao, Ruey-Hsin Liu, Ming-Ta Lei
  • Patent number: 10660358
    Abstract: The present invention provides a method to convert the intrinsic sugar of a juice into indigestible oligosaccharides (such as, low-polymerization fructose and sorbitol). The present method comprises using a Zymomonas mobilis biomass and fructosyltransferase as well as pressure treatment. Taking advantage of the present method, the drawbacks of drinking juices, such as too many sugar and calorie intake can be obviated, and thereby the present invention can offer healthier option to the consumers.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: May 26, 2020
    Assignee: Food Industry Research and Development Institute
    Inventors: Chung-Liang Chu, Ta-Ching Cheng, Yu-Chuan Tseng
  • Patent number: 10658241
    Abstract: A method of fabricating an integrated circuit includes the following steps. A first reticle is used to form a first pattern, wherein the first pattern includes a first feature and a first jog part protruding from and orthogonal to the first feature. A second reticle is used to form a second pattern, wherein the second pattern includes a second feature, and the first feature is between the second feature and the first jog part. A third reticle is used to form a third pattern, wherein the third pattern includes a third-one feature overlapping the first jog part and a third-two feature overlapping the second feature.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: May 19, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Liang Chu, Yu-Ruei Chen, Yu-Hsiang Lin
  • Publication number: 20200144483
    Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, wherein the ring of MTJ region comprises a first MTJ, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, each of the metal interconnect patterns includes a first metal interconnection connected to the first MTJ directly.
    Type: Application
    Filed: December 31, 2019
    Publication date: May 7, 2020
    Inventors: Chung-Liang Chu, Jian-Cheng Chen, Yu-Ping Wang, Yu-Ruei Chen
  • Publication number: 20200144485
    Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the ring of MTJ region comprises an octagon and the ring of MTJ region includes a first MTJ region and a second MTJ region extending along a first direction, a third MTJ region and a fourth MTJ region extending along a second direction, a fifth MTJ region and a sixth MTJ region extending along a third direction, and a seventh MTJ region and an eighth MTJ region extending along a fourth direction.
    Type: Application
    Filed: January 9, 2020
    Publication date: May 7, 2020
    Inventors: Chung-Liang Chu, Jian-Cheng Chen, Yu-Ping Wang, Yu-Ruei Chen
  • Patent number: 10566520
    Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.
    Type: Grant
    Filed: July 8, 2018
    Date of Patent: February 18, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Liang Chu, Jian-Cheng Chen, Yu-Ping Wang, Yu-Ruei Chen
  • Patent number: 10523057
    Abstract: The present application provides a wireless charging module and a modularized sensing device therewith. A first charging unit is disposed around the inside of the wireless charging module for wirelessly charging a sensing module. Without introducing a transmission line as an electricity transmitting medium, the sensing module can be directly disposed inside and charged by the wireless charging module, which improves flexibility of implementation. Further, since the first charging unit is configured to surround the inside of the wireless charging module shaped as a bowl structure, the sensing module can be simply disposed into the bowl structure and wirelessly charged by the surrounding first charging units, which saves the inconvenience of setting the sensing module to a specific location or area for stable wireless charging and increases effective charging angles.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: December 31, 2019
    Assignee: National Chung-Shan Institute of Science and Technology
    Inventors: Po-Chun Yang, Chun-Liang Chu, Yu-San Lin, Yu-Cheng Chang
  • Publication number: 20190378971
    Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.
    Type: Application
    Filed: July 8, 2018
    Publication date: December 12, 2019
    Inventors: Chung-Liang Chu, Jian-Cheng Chen, Yu-Ping Wang, Yu-Ruei Chen
  • Publication number: 20190363165
    Abstract: A semiconductor device includes a semiconductor substrate, a gate dielectric, a gate electrode and a pair of source/drain regions. The gate dielectric is disposed in the semiconductor substrate having a concave profile that defines an upper boundary lower than an upper surface of the semiconductor substrate. The gate electrode is disposed over the gate dielectric. The pair of source/drain regions are disposed on opposing sides of the gate dielectric.
    Type: Application
    Filed: May 23, 2018
    Publication date: November 28, 2019
    Inventors: TA-YUAN KUNG, RUEY-HSIN LIU, CHEN-LIANG CHU, CHIH-WEN YAO, MING-TA LEI
  • Publication number: 20190348239
    Abstract: The disclosure provides a hydraulic switch including a casing, a first cable, a second cable, an electrically conductive piston and a first magnetic conductive component. The casing has a chamber and a liquid channel connected to the chamber. The first cable is disposed through the casing, and the first electrical connection portion of that is located in the chamber. The second cable is disposed through the casing, and a second electrical connection portion of that is located in the chamber. The electrically conductive piston movably is disposed in the chamber. When the electrically conductive piston is in an electrically connected position, the electrically conductive piston is in electrical contact with the first electrical connection portion and the second electrical connection portion. The first magnetic conductive component is configured to provide a magnetic force to move the electrically conductive piston toward an electrically disconnected position.
    Type: Application
    Filed: April 30, 2019
    Publication date: November 14, 2019
    Inventor: En-Liang CHU
  • Patent number: 10374006
    Abstract: The present invention provides a magnetic random access memory (MRAM) structure, the MRAM structure includes a transistor including a gate, a source and a drain, and a magnetic tunnel junction (MTJ) device, the MTJ device includes at least one free layer, an insulating layer and a fixed layer, the insulating layer is disposed between the free layer and the fixed layer, and the free layer is located above the insulating layer. The free layer of the MTJ device is electrically connected to a bit line (BL). The fixed layer of the MTJ device is electrically connected to the source of the transistor, and the drain of the transistor is electrically connected to a sense line (SL). And a first conductive via, directly contacting the MTJ device, the material of the first conductive via comprises tungsten.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: August 6, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Liang Chu, Yu-Ping Wang, Yu-Ruei Chen
  • Publication number: 20190237485
    Abstract: Some embodiments of the present disclosure relate to a method of forming a transistor. The method includes forming a gate dielectric over a substrate and forming a gate over the gate dielectric. The gate includes polysilicon extending between a first outermost sidewall and a second outermost sidewall of the gate. A mask is formed over the gate. The mask exposes a first gate region extending to the first outermost sidewall and covers a second gate region extending between the first gate region and the second outermost sidewall. Dopants are selectively implanted into the first gate region according to the mask. Source and drain regions are formed within the substrate. The source region and the drain region are asymmetric with respect to an interface of the first gate region and the second gate region and extend to substantially equal distances past the first and second outermost sidewalls of the gate, respectively.
    Type: Application
    Filed: April 12, 2019
    Publication date: August 1, 2019
    Inventors: Chen-Liang Chu, Chih-Wen Albert Yao, Ruey-Hsin Liu, Ming-Ta Lei
  • Patent number: 10355048
    Abstract: An isolation structure is disposed between fin field effect transistors of a magnetic random access memory (MRAM) device. The isolation structure includes a fin line substrate, having a trench crossing the fin line substrate. An oxide layer is disposed on the fin line substrate other than the trench. A liner layer is disposed on an indent surface of the trench. A nitride layer is disposed on the liner layer, partially filling the trench. An oxide residue is disposed on the nitride layer within the trench at a bottom portion of the trench. A gate-like structure is disposed on the oxide layer and also fully filling the trench.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: July 16, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Chung-Liang Chu, Yu-Ruei Chen, Hung-Yueh Chen, Yu-Ping Wang
  • Publication number: 20190194786
    Abstract: The present invention discloses a kind of hardfacing alloy, which can be applied onto a workpiece's surface by any one surface treatment process in accordance with material, dimensions, and required properties of the workpiece. For example, this novel hardfacing material can be heated to a fully melted state or a partially melted state by using different types of heat sources, such that the melted hardfacing material can be coated onto the surface of any one workpiece to form a protective layer or a surface modification layer. As a result, the workpiece having the surface coating layer with superior characteristics exhibits outstanding functional performances and has a long service time.
    Type: Application
    Filed: December 22, 2017
    Publication date: June 27, 2019
    Inventors: MING-HAO CHUANG, YUN-SHENG WU, JUNE-LIANG CHU, Dimas Rizky Widagdyo, TIEN-HAO CHANG, SIOU-YU HUANG
  • Publication number: 20190181046
    Abstract: A method of fabricating an integrated circuit includes the following steps. A first reticle is used to form a first pattern, wherein the first pattern includes a first feature and a first jog part protruding from and orthogonal to the first feature. A second reticle is used to form a second pattern, wherein the second pattern includes a second feature, and the first feature is between the second feature and the first jog part. A third reticle is used to form a third pattern, wherein the third pattern includes a third-one feature overlapping the first jog part and a third-two feature overlapping the second feature.
    Type: Application
    Filed: December 12, 2017
    Publication date: June 13, 2019
    Inventors: Chung-Liang Chu, Yu-Ruei Chen, Yu-Hsiang Lin