Abstract: A semiconductor device includes a substrate, an isolation structure, a first gate structure, a second gate structure, a first slot contact structure, a first gate contact structure, and a second gate contact structure. The substrate includes a first active region and a second active region elongated in a first direction respectively. The first gate structure, the second gate structure, and the first slot contact structure are continuously elongated in a second direction respectively. The first gate contact structure and the second gate contact structure are disposed at two opposite sides of the first slot contact structure in the first direction respectively.

Abstract: A semiconductor device includes a semiconductor substrate, a gate dielectric, a gate electrode, and a pair of source/drain regions. The gate dielectric is disposed in the semiconductor substrate having an upper boundary lower than an upper surface of the semiconductor substrate, and an upper surface flush with the upper surface of the semiconductor substrate. The gate electrode is disposed over the gate dielectric having a first section over the upper boundary of the gate dielectric and a second section over the upper surface of the gate dielectric. The second section partially covers and partially exposes the upper surface of the gate dielectric. The pair of source/drain regions are disposed on opposing sides of the gate dielectric.

Abstract: A bicycle brake lever includes a main body, a brake assembly, and a valve. The main body includes a casing and a cover mounted on the casing. The casing has a storage chamber and a hydraulic chamber. The brake assembly includes a lever, a link, and a piston. The lever is pivotally disposed on the casing, the link connects the lever and the piston, the link is disposed through the cover, the piston is movably located in the hydraulic chamber and has an inner channel in fluid communication with the storage chamber. The valve is movably disposed on the casing. The valve is partially located in the hydraulic chamber. When the piston is moved from an initial position to a sealed position, the valve blocks the inner channel of the piston, such that the hydraulic chamber is not in fluid communication with the storage chamber.

Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.

Abstract: The present application reveals a system for computing and a method for arranging nodes thereof, which is applied for a remote host connected with a plurality of computing nodes divided to a plurality of first nodes and second nodes due to a first computing mode and a second computing mode. After the remote host receives a job, the remote host evaluates the computing nodes in accordance with the job and a corresponding priority weight parameter to generate a job beginning data to set the first nodes or the second nodes and to proceed the job. While setting the first or the second nodes, the remote host provides the corresponding system image to the corresponding nodes; while the first or the second nodes are full in resource arrangement, the empty nodes will be converted to the supplement nodes with the corresponding system image from the remote host.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate of a first conductivity; a first region of the first conductivity formed in the substrate; a second region of the first conductivity formed in the first region, wherein the second region has a higher doping density than the first region; a source region of a second conductivity formed in the second region; a drain region of the second conductivity formed in the substrate; a pickup region of the first conductivity formed in the second region and adjacent to the source region; and a resist protective oxide (RPO) layer formed on a top surface of the second region. An associated fabricating method is also disclosed.

Abstract: A method to form a transistor device with a recessed gate structure is provided. In one embodiment, a gate structure is formed overlying a device region and an isolation structure. The gate structure separates a device doping well along a first direction with a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A pair of source/drain regions in is formed the device region on opposite sides of the gate structure. A sidewall spacer is formed extending along sidewalls of the gate structure, where a top surface of the sidewall spacer is substantially flush with the top surface of the gate structure. A resistive protection layer is then formed on the sidewall spacer and covering the pair of recess regions.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.

Abstract: A semiconductor device includes a substrate having a magnetic random access memory (MRAM) region and a logic region, a first metal interconnection on the MRAM region, a second metal interconnection on the logic region, a stop layer extending from the first metal interconnection to the second metal interconnection, and a magnetic tunneling junction (MTJ) on the first metal interconnection. Preferably, the stop layer on the first metal interconnection and the stop layer on the second metal interconnection have different thicknesses.

Abstract: A fin transistor structure is provided. The fin transistor structure includes a first substrate. An insulation layer is disposed on the first substrate. A plurality of fin structures are disposed on the insulation layer. A supporting dielectric layer fixes the fin structures at the fin structures at waist parts thereof. A gate structure layer is disposed on the supporting dielectric layer and covers a portion of the fin structures.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.

Abstract: A transistor device with a recessed gate structure is provided. In some embodiments, the transistor device comprises a semiconductor substrate comprising a device region surrounded by an isolation structure and a pair of source/drain regions disposed in the device region and laterally spaced apart one from another in a first direction. A gate structure overlies the device region and the isolation structure and arranged between the pair of source/drain regions. The gate structure comprises a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A channel region is disposed in the device region underneath the gate structure. The channel region has a channel width extending in the second direction from one of the recess regions to the other one of the recess regions.

Abstract: The disclosure provides a hybrid magnet structure which includes two dipole magnets assemblies arranged oppositely, and each dipole magnet assembly includes a permanent magnet, two iron cores, and a moveable magnetic field shunt element. The hybrid magnet structure is adapted to focus particle beams of different positions by applying an adjustable gradient magnetic field in the horizontal or vertical direction of the particle beam. By passing the charged particle beams through the gradient magnetic field established between the two dipole magnets, the aspect of focusing the charged particle beam is achieved. In addition, the intensity of the gradient magnetic field can be altered by adjusting the gap between the movable magnetic field shunt element and the permanent magnet, thereby controlling the particle beam size on a specific axis for different energies or masses of the charge particles.

Abstract: A fin transistor structure is provided. The fin transistor structure includes a first substrate. An insulation layer is disposed on the first substrate. A plurality of fin structures are disposed on the insulation layer. A supporting dielectric layer fixes the fin structures at the fin structures at waist parts thereof. A gate structure layer is disposed on the supporting dielectric layer and covers a portion of the fin structures.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.

Abstract: Provided herein are methods for manufacturing a multilayer circuit structure having embedded circuits and the multilayer circuit structure made thereby. A substrate having at least one existing circuit on the surface is provided, then a dielectric layer is formed to cover the existing circuit. A metal layer is subsequently formed on the dielectric layer. The metal layer is made into a metal mask with a pattern by photoimaging, then the pattern is transferred to the dielectric layer underneath by plasma etching to create multiple trenches and pads at the same time. After vias are made at the pads, a conductive metal is deposited into the trenches and vias to form an embedded trace layer with excess conductive metal in the dielectric layer. The excess conductive metal is removed to obtain a new circuit embedded in the dielectric layer and is coplanar with the surface of the dielectric layer.

Abstract: Provided herein are methods for manufacturing a multilayer circuit structure having embedded circuits and the multilayer circuit structure made thereby. A substrate having at least one existing circuit on the surface is provided, then a dielectric layer is formed to cover the existing circuit. A metal layer is subsequently formed on the dielectric layer. The metal layer is made into a metal hard mask with a pattern by photoimaging, then the pattern is transferred to the dielectric layer underneath by plasma etching to create trenches and pads for vias at the same time. After vias are made on the pads, a conductive metal is deposited into the trenches and vias to form an embedded trace layer in the respective dielectric layer. The excess conductive metal is removed to obtain a new circuit embedded in the dielectric layer and is coplanar with the surface of the dielectric layer.

Abstract: The disclosure provides a hydraulic switch including a casing, a first cable, a second cable, an electrically conductive piston and a first magnetic conductive component. The casing has a chamber and a liquid channel connected to the chamber. The first cable is disposed through the casing, and the first electrical connection portion of that is located in the chamber. The second cable is disposed through the casing, and a second electrical connection portion of that is located in the chamber. The electrically conductive piston movably is disposed in the chamber. When the electrically conductive piston is in an electrically connected position, the electrically conductive piston is in electrical contact with the first electrical connection portion and the second electrical connection portion. The first magnetic conductive component is configured to provide a magnetic force to move the electrically conductive piston toward an electrically disconnected position.

Abstract: A bicycle hydraulic assembly includes a casing, a first piston, and a second piston. The casing has a hydraulic chamber, an inlet channel, and an outlet channel connected to the hydraulic chamber. The first piston is located in the hydraulic chamber. The second piston is sleeved on the first piston. The second piston has a first end portion and a second end portion opposite to each other. The first end portion is wider than the second end portion located farther away from the inlet channel than the first end portion. When the first piston is moved a distance smaller than a threshold distance, the first piston is moved relative to the second piston while the second piston is stationary relative to the casing. When the first piston is moved a distance greater than the threshold distance, the first piston forces the second piston to move relative to the casing.

Abstract: The present application reveals a system for computing and a method for arranging nodes thereof, which is applied for a remote host connected with a plurality of computing nodes divided to a plurality of first nodes and second nodes due to a first computing mode and a second computing mode. After the remote host receives a job, the remote host evaluates the computing nodes in accordance with the job and a corresponding priority weight parameter to generate a job beginning data to set the first nodes or the second nodes and to proceed the job. While setting the first or the second nodes, the remote host provides the corresponding system image to the corresponding nodes; while the first or the second nodes are full in resource arrangement, the empty nodes will be converted to the supplement nodes with the corresponding system image from the remote host.