Abstract: An Ethernet physical-layer circuit corresponding to a first port is connected to a first link partner device through the first port and a first Ethernet cable. The Ethernet physical-layer circuit and other physical-layer circuits all employ an output oscillation signal of a crystal oscillator to respectively generate clock waveforms, and they are configured in a master mode when the crosstalk noise is converged and compensated.

Abstract: An electronic system sharing power of a doorbell includes a switch circuit and an electronic device. The first and second connection terminals of the switch circuit are respectively coupled to two doorbell contacts. The second and third connection terminals of the switch circuit are respectively coupled to two ends of a doorbell. Two power terminals of the electronic device are respectively coupled to two switch contacts. A function circuit of the electronic device is coupled between the two power terminals. In a normal mode, the first connection terminal is conducted to the second connection terminal inside the switch circuit, and the two power terminals are disconnected from each other by a doorbell actuating unit of the electronic device. In a ringing mode, the doorbell actuating unit short-circuits the two power terminals, and the first connection terminal is conducted to the third connection terminal inside the switch circuit.

Abstract: A method for receiving data includes receiving a transmission signal through a channel, adjusting the intensity of the transmission signal to generate an adjusted transmission signal according to an analog gain level, converting the adjusted transmission signal into a digital signal, filtering the digital signal to generate a filtered signal according to a set of filter coefficients, and adjusting intensity of the filtered signal according to a digital gain level. The method further includes, in a training mode, estimating a transmission condition of the channel and adjusting the analog gain level and the digital gain level according to the transmission condition for obtaining convergent values for the set of filter coefficients before the training mode ends, and in a data mode, performing a gain adjustment operation to adjust the analog gain level and to adjust the digital gain level according to the adjustment made to the analog gain level.

Abstract: A signal transceiver circuit, a method of operating a signal transmitting circuit, and a method of setting a delay circuit are provided. The signal transceiver circuit is used to send an output signal and receive an input signal, and includes: a delay circuit for delaying a first clock to generate a second clock; a first digital-to-analog converter (DAC) for converting a first digital signal into the output signal according to the first clock; a second DAC for converting the first digital signal into an echo cancellation signal according to the second clock; an analog front-end circuit for receiving the input signal and the echo cancellation signal and generating an analog signal; and an analog-to-digital converter (ADC) for converting the analog signal into a second digital signal.

Abstract: Parameter calibration method for calibrating multiple parameters corresponding to multiple electronic components to be calibrated in a circuit, including steps: (A) turning off all of the electronic components to be calibrated and selecting a first electronic component from the electronic components to be calibrated as an electronic component being calibrated; (B) turning on the electronic component being calibrated and performing a calibration procedure on the electronic component being calibrated to determine a setting value of a parameter corresponding to the electronic component being calibrated; and (C) selecting a second electronic component from the electronic components to be calibrated as the electronic component being calibrated and performing step (B).

Abstract: A transceiver circuit includes an ADC and an echo-cancellation circuit, wherein the echo-cancellation circuit includes a steady circuit, a transient circuit and an output circuit. In the operations of the transceiver circuit, the ADC is configured to perform an analog-to-digital conversion operation on an analog input signal to generate a digital input signal. The steady circuit is configured to generate a steady echo response according to a transmitting signal. The transient circuit is configured to generate an echo response adjustment signal according to a phase change of a clock signal used by the transmitting signal. The output circuit is configured to generate an output signal according to the digital input signal, the steady echo response, and the echo response adjustment signal.

Abstract: Compounds are provided having the structure of Formula (I): or a pharmaceutically acceptable isomer, racemate, hydrate, solvate, isotope, or salt thereof, wherein A, B, L, R3, R4, R5, R6, R8, m and n are as defined herein. Such compounds modulate the opioid receptor, particulare the mu-opioid receptor (MOR) and/or the kappa-opioid receptor (KOR), and/or the delta-opioid receptor (DOR). Products containing such compounds, as well as methods for their use and preparation, are also provided.

Abstract: A method and a measuring apparatus for measuring noise of a device under test (DUT) is provided, wherein the DUT is connected to a link partner (LP) device via a cable, and the measuring apparatus is coupled to the DUT and LP device. The method includes: controlling the LP device to transmit a far-end data sequence to the DUT according to transmission data; controlling the DUT to recover the transmission data for generating aided-data sequence according to the transmission data, wherein the aided-data sequence is configured to perform cancellation with a received far-end data sequence to generate a cancellation result; generating a first noise value and a second noise value in a first training phase and a second training phase, respectively; and estimating noise from at least one circuit according to the first noise value and the second noise value.

Abstract: A decision feedback equalizer includes: a feedforward equalizer, a feedback equalizer, a slicer and a decision adjustment unit. The feedforward equalizer is arranged to generate a feedforward output signal based on an input signal. The feedback equalizer is coupled to the feedforward equalizer and arranged to generate a feedback output signal according to a decision output signal. The slicer is coupled to the feedforward equalizer and the feedback equalizer, and is controllable by a decision adjustment parameter, wherein the slicer is arranged to perform a slicer decision on a sum of the feedforward output signal and the feedback output signal, thereby generating the decision output signal. The decision adjustment unit is coupled to the slicer, and is arranged to adjust the decision adjustment parameter according to a sleep state of a communication device in which the decision feedback equalizer is disposed.

Abstract: A decision feedback equalizer includes: a feedforward equalizer, a feedback equalizer, a slicer and a decision adjustment unit. The feedforward equalizer is arranged to generate a feedforward output signal based on an input signal. The feedback equalizer is coupled to the feedforward equalizer and arranged to generate a feedback output signal according to a decision output signal. The slicer is coupled to the feedforward equalizer and the feedback equalizer, and is controllable by a decision adjustment parameter, wherein the slicer is arranged to perform a slicer decision on a sum of the feedforward output signal and the feedback output signal, thereby generating the decision output signal. The decision adjustment unit is coupled to the slicer, and is arranged to adjust the decision adjustment parameter according to a sleep state of a communication device in which the decision feedback equalizer is disposed.

Abstract: A semiconductor device includes a bottom electrode; a magnetic tunneling junction (MTJ) element over the bottom electrode; a top electrode over the MTJ element; and a sidewall spacer abutting the MTJ element, wherein at least one of the bottom electrode, the top electrode, and the sidewall spacer includes a magnetic material.

Abstract: A one-time programmable (OTP) memory device includes a first memory cell, which further includes a first source line extending along a first direction on a substrate, a first word line extending along the first direction on one side of the first source line, a second word line extending along the first direction on another side of the first source line, a first diffusion region extending along a second direction adjacent to two sides of the first word line and the second word line, and a first metal interconnection connecting the first word line and the second word line.

Abstract: The present disclosure provides a gas purge device and a gas purge method for purging a wafer container to clean wafers. The gas purge device includes a first nozzle and a gas gate. The first nozzle is coupled to a front-opening unified pod (FOUP) through a first port of the FOUP. The gas gate is coupled to the first nozzle via a first pipe. The gas gate includes a first mass flow controller (MFC), a second MFC, and a first switch unit. The first MFC is configured to control a first flow of a first gas. The second MFC is configured to control a second flow of a second gas. The first switch unit is coupled to the first MFC and the second MFC, and is configured to provide the first gas to the first nozzle through the first pipe or receive the second gas from the first nozzle through the first pipe according to a process configuration.

Abstract: A receiver includes an equalizer circuit, a radio frequency interference cancellation circuitry, and a channel estimation circuitry. The equalizer circuit is configured to process a first data signal according to a control signal, in order to generate a second data signal. The radio frequency interference cancellation circuitry is configured to detect a radio frequency interference signal according to the second data signal to generate radio frequency interference information, and to output a correction signal according to the radio frequency interference information, in order to correct the second data signal. The channel estimation circuitry configured to analyze a plurality of sets of signal components in the second data signal, and to utilize a power ratio of one of the plurality of sets of signal components to generate the control signal.

Abstract: A mechanical multi-rod disc brake contains: a braking unit including an engagement structure having two bases, two swing arms, two wear-resistant sleeves, and two fixing pistons between which an accommodation space is defined so as to accommodate a stop disc. A respective one wear-resistant sleeve has a respective one fixing piston. A drive unit includes a multi-rod structure, and a respective one rotary shaft is rotatably connected with a respective one driven bolt rotatably connected with a respective one driving member via a respective one connection portion. A respective one joining element has a receiving hole rotatably connected with of a first extension of a first connection stein or a second extension of a second connection stein. Each of the first extension and the second extension has a resilient element, and the first and second extensions are connected with a brake cable via the first and second apertures.

Abstract: The invention provides a speaker recognition method, which comprises three stages of recognition. The first-stage recognition is to detect whether a text-dependent test statement is a spoofing attack of the replay. The second-stage recognition is to detect whether a text-independent test statement is a spoofing attack of the synthetic speech. The third-stage recognition is to judge which registered speaker speaks the text-independent test statement by a speaker recognition system. If it is not spoken by the registered speaker, it is directed to an imposter. The first two stages use different features with different binary classifiers, and the third stage uses a complex classifier to determine the text-independent is spoken by target or imposter through Ensemble Learning and Unanimity Rule with conditional retry mechanism. Therefore, the rate of blocking the target can be effectively reduced without losing the rate of blocking the impostor.

Abstract: A signal processing device includes a decision feedback equalizer and a coefficient adjusting circuit. The decision feedback equalizer includes a first equalizer configured to perform filtering on a first signal according to a set of first coefficients to generate a first filtered signal. The set of first coefficients includes multiple first coefficients. The coefficient adjusting circuit is configured to adaptively adjust one or more of the first coefficients according to an error signal. A limit operation of the first coefficients is selectively performed. When the limit operation of the first coefficients is performed, at least one of the first coefficients is set to a first predetermined value to generate a set of limited first coefficients.

Abstract: An in-memory computing device including a plurality of memory cell arrays and a plurality of sensing amplifiers are provided. The memory cell arrays respectively receive a plurality of input signals. The input signals are divided into a plurality of groups. The groups respectively have at least one partial input signal. The at least one partial input signal of each of the groups has a same value. Numbers of the at least one partial input signal in the groups sequentially form a geometric sequence with a common ration equal to 2. The memory cell arrays respectively provide a plurality of weightings, and perform multiply-add operations respectively according to the received input signals and the weightings to generate a plurality of computation results. The sensing amplifiers respectively generate a plurality of sensing results according to the computation results.

Abstract: A transmission circuit includes a data input pin, a serial-to-parallel converter, an interface decoder, a parallel-to-serial converter, and a processor circuit. The serial-to-parallel converter is electrically coupled to the data input pin. The serial-to-parallel converter converts a plurality of data signals received by the first data input pin into a set of parallel data signals. The interface decoder is electrically coupled to the serial-to-parallel converter. The interface decoder decodes the set of parallel data signals to generate a set of decoded data signals for parallel transmission. The parallel-to-serial converter is electrically coupled to the interface decoder. The parallel-to-serial converter converts the set of decoded data signals into a plurality of input data signals for serial transmission. The processor circuit is electrically coupled to the parallel-to-serial converter. The processor circuit receives and processes the plurality of input data signals.

Abstract: A decision feedback equalizer for generating an output signal according to an input signal includes: a feedforward equalizer, a feedback equalizer and a weight coefficient control unit. The feedforward equalizer includes a plurality of tapped delay lines and is controlled by a set of first weight coefficients. The feedback equalizer includes a plurality of tapped delay line and is controlled by a set of second weight coefficients. The weight coefficient control unit is employed to selectively adjust at least one of the set of first weight coefficients and determine a set of first boundary values for at least one of the set of second weight coefficients. When the at least one of the set of second weight coefficients does not exceed the set of first boundary values, the weight coefficient control unit increments the at least one of the set of first weight coefficients.