Abstract: The photochromic helmet visor includes a transparent piece, an adhesive layer attached to the transparent piece, a flexible base layer attached to the adhesive layer, a self-repairing layer attached to the flexible base layer, and a number of photochromic elements integrated with the flexible base layer or the self-repairing layer. The self-repairing layer includes a. PU layer and a. Siloxane layer attached to the PU layer. The photochromic elements are integrated with the flexible base layer or the self-repairing layer. The flexible base layer is made of PU, TPU, PVC, or PET, and may be tightly and smoothly joined to the transparent piece along with the adhesive layer. The self-repairing layer allows self-repairing to scratches or abrasions under a high temperature, thereby preventing the malfunction of the photochromic elements out of wear and usage and the resulted constant replacement, and enhancing the visor's durability.

Abstract: The present invention discloses a DAC method having signal calibration mechanism. A first conversion circuit generates a first analog signal according to an input digital signal. A second conversion circuit generates a second analog signal according to the input digital signal and a pseudo-noise digital signal. An echo transmission circuit processes a signal on an echo path to generate an echo signal. A first and a second calibration circuits generate a first and a second calibration signals. A calibration parameter calculation circuit performs calculation according to a difference between the echo signal and a sum of the first and the second calibration signals and related path information to generate a first and a second offsets. The first and the second calibration circuits converge first and second response coefficients and update a first and a second codeword offset tables according to the first and the second offsets.

Abstract: A decoding method adopting an algorithm with weight-based adjusted parameters and a decoding system are provided. The decoding method is applied to a decoder. M×N low density parity check codes (LDPC codes) having N variable nodes and M check nodes are generated from input signals. In the decoding method, information of the variable nodes and the check nodes is initialized. The information passed from the variable nodes to the check nodes is formed after multiple iterations. After excluding a connection to be calculated, a product of the remaining connections between the variable nodes and the check nodes is calculated. Next, an estimated first minimum or an estimated second minimum can be calculated with multi-dimensional parameters. The information passed from the check nodes to the variable nodes can be updated for making a decision.

Abstract: A method for cancelling radio frequency interference (RFI) and a communication system thereof are provided. In the communication system, digital signals of a frequency domain are converted from analog signals and received by the communication system generally carry RFI, and the signals are processed by an equalizer and a far-end crosstalk canceller. Then, for preventing erroneous signals from forming due to an occurrence of a notch, masking parameters applied to the equalizer and the far-end crosstalk canceller are modified for not processing frequency bands that are RFI-affected. The frequency bands can be ignored by masking corresponding bins in the frequency domain after a fast Fourier transformation. The signals processed by the equalizer and the far-end crosstalk canceller are then outputted to an RFI canceller, and the signals with RFI cancellation can be obtained.

Abstract: A stereoscopic warehousing equipment comprising a conveying line assembly, a left storage assembly located at left end of the conveying line assembly, a right storage assembly located on tright end of the conveying line assembly, and a transferring carrying assembly arranged above the conveying line assembly and located between the left storage assembly and the right storage assembly, wherein the conveying line assembly comprising a conveying line mounting frame, an upper speed-chain conveying line and a lower speed-chain conveying line, wherein the conveying line mounting frame is provided with a lifting conveying platform located at front end of the upper and lower speed-chain conveying lines, wherein the lifting conveying platform comprising an electric lifting platform and a middle speed-chain conveying line, wherein the transferring carrying assembly comprising a transferring carrying portal frame, a horizontal driving linear module, a left carrying mechanism and a right carrying mechanism.

Abstract: Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a dielectric layer including a top surface, a plurality of magneto-resistive memory cells disposed in the dielectric layer and including top electrodes, a first etch stop layer disposed over the dielectric layer, a common electrode extending through the first etch stop layer to be in direct contact with the top electrodes, and a second etch stop layer disposed on the first etch stop layer and the common electrode.

Abstract: This paper presents a practical method for measuring the impact of multiple marketing events on sales, including marketing events that are not traditionally trackable. The technique infers which of several competing media events are likely to have caused a given conversion. The method is tested using hold-out sets, and also a live media experiment for determining whether the method can accurately predict television-generated web conversions.

Abstract: Provided herein are opioid receptor modulators and pharmaceutical compositions comprising said compounds.

Abstract: An electronic device includes a processor, a battery, a charging circuit, a controller, and an arithmetic logic unit. The processor is capable of operating at a preset frequency or a low frequency. The charging circuit is electrically connected to an external power supply and a battery and transmits a disconnection signal and to be powered by the battery when the external power supply and the charging circuit are changed from a connected state to a disconnected state. The controller is configured to transmit a first control signal when the external power supply and the charging circuit are changed from the connected state to the disconnected state. The arithmetic logic unit is configured to transmit a frequency reduction signal to the processor according to the disconnection signal and the first control signal, so that the processor reduces the preset frequency to the low frequency and operates at the low frequency.

Abstract: A stereoscopic warehousing equipment comprising a conveying line assembly, a left storage assembly located at left end of the conveying line assembly, a right storage assembly located on right end of the conveying line assembly, and a transferring carrying assembly arranged above the conveying line assembly and located between the left storage assembly and the right storage assembly, wherein the conveying line assembly comprising a conveying line mounting frame, an upper speed-chain conveying line and a lower speed-chain conveying line, wherein the conveying line mounting frame is provided with a lifting conveying platform located at front end of the upper and lower speed-chain conveying lines, wherein the lifting conveying platform comprising an electric lifting platform and a middle speed-chain conveying line, wherein the transferring carrying assembly comprising a transferring carrying portal frame, a horizontal driving linear module, a left carrying mechanism and a right carrying mechanism.

Abstract: The present invention discloses a DAC method having signal calibration mechanism is provided. Operation states of current sources are controlled to generate an output analog signal by a DAC circuit according to a codeword of an input digital signal. An echo signal is generated by an echo transmission circuit according to the output analog signal. The codeword is mapped to generate an offset signal by a calibration circuit according to a codeword offset mapping table. The offset signal is processed to generate an echo-canceling signal by an echo-canceling circuit. By a calibration parameter calculation circuit, offset amounts are generated according to a difference between the echo signal and the echo-canceling signal, the offset amounts are grouped to perform statistic operation according to the operation states and current offset values are calculated according to calculation among groups and converted to codeword offset values to update the codeword offset mapping table.

Abstract: The present invention discloses a DAC method having signal calibration mechanism is provided. Operation states of current sources are controlled to generate an output analog signal by a DAC circuit according to a codeword of an input digital signal. An echo signal is generated by an echo transmission circuit according to the output analog signal. The codeword is mapped to generate an offset signal by a calibration circuit according to a codeword offset mapping table. The offset signal is processed to generate an echo-canceling signal by an echo-canceling circuit. By a calibration parameter calculation circuit, offset amounts are generated according to a difference between the echo signal and the echo-canceling signal, the offset amounts are grouped to perform statistic operation according to the operation states and current offset values are calculated according to calculation among groups and converted to codeword offset values to update the codeword offset mapping table.

Abstract: A digital-to-analog converter circuit generates an analog transmitted signal according to a digital transmitted signal. A first echo canceller circuit generates a first echo cancelling signal according to the digital transmitted signal. A processor circuit generates an analog processed signal according to the analog transmitted signal, the first echo cancelling signal, and a received signal. An analog-to-digital converter circuit generates a digital value according to the analog processed signal and two slicer levels of a plurality of slicer levels. A storage circuit stores a look-up table. The look-up table records an offset value corresponding to the digital value. The storage circuit further outputs a first output signal according to the digital value and the offset value. The offset value is updated according to an error value associated with the first output signal.

Abstract: A method includes: generating a first signal according to a digital signal; filtering the first signal according to first filter coefficients of first filter to generate a second signal; adding a first reference signal with the second signal to generate a third signal; performing digital-to-analog conversion according to the first and third signals to generate and output an echo signal; performing analog-to-digital conversion according to the echo signal to generate a fourth signal; generating a fifth signal according to the digital signal and the fourth signal; and updating the first filter coefficients according to the fifth signal.

Abstract: In a method of manufacturing a semiconductor device, a cell structure is formed. The cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack disposed on the bottom electrode and a hard mask layer disposed on the MTJ stack. A first insulating cover layer is formed over sidewall of the MTJ stack. A second insulating cover layer is formed over the first insulating cover layer and the hard mask layer. A first interlayer dielectric (ILD) layer is formed. The hard mask layer is exposed by etching the first ILD layer and the second insulating cover layer. A second ILD layer is formed. A contact opening is formed in the second ILD layer by patterning the second ILD layer and removing the hard mask layer. A conductive layer is formed in the contact opening so that the conductive layer contacts the MTJ stack.

Abstract: A signal processing method is provided. The signal processing method is used in a Gigabit Ethernet system including a device under test (DUT) and a link partner (LP), and includes the following steps. Firstly, an interference detector is configured to detect whether the Gigabit Ethernet system is interfered by other signal sources. Next, a physical layer (PHY) of the DUT or a PHY of the LP is used to, in response to the Gigabit Ethernet system being interfered by the other signal sources, set a request signal indicating whether or not the physical layer enters a low power idle (LPI) mode as FALSE. Which PHY of the DUT and the LP is used to set the request signal indicating whether or not the PHY enters the LPI mode as FALSE depends upon which one of the DUT and the LP is provided with the interference detector.

Abstract: A channel estimation method is configured to estimate a channel length. The method includes the following operations: receiving an input signal; summing the input signal and an analog echo cancelation signal decrease an echo of the input signal, and generate a first signal according to a result of the summation; providing an analog gain value to the first signal to generate a second signal; performing an analog-to-digital conversion to the second signal to generate a third signal; obtaining a ratio according to an energy of a first frequency and an energy of a second frequency of the third signal; and estimating the channel length according to the ratio, and setting the analog gain value according to the estimated channel length.

Abstract: A method for receiving data includes receiving a transmission signal through a channel, adjusting the intensity of the transmission signal to generate an adjusted transmission signal according to an analog gain level, converting the adjusted transmission signal into a digital signal, filtering the digital signal to generate a filtered signal according to a set of filter coefficients, and adjusting intensity of the filtered signal according to a digital gain level. The method further includes, in a training mode, estimating a transmission condition of the channel and adjusting the analog gain level and the digital gain level according to the transmission condition for obtaining convergent values for the set of filter coefficients before the training mode ends, and in a data mode, performing a gain adjustment operation to adjust the analog gain level and to adjust the digital gain level according to the adjustment made to the analog gain level.

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, an interconnect structure, a memory cell and a conductive via. The semiconductor substrate has a first side and a second side opposite to the first side. The gate structure is disposed over the first side of the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate aside the gate structure. The interconnect structure is disposed over the first side of the semiconductor substrate and electrically connected to the source region. The memory cell is disposed over the second side of the semiconductor substrate and electrically connected to the drain region. The conductive via is disposed in the semiconductor substrate between the drain region and the memory cell and electrically connects the drain region and the memory cell.

Abstract: A semiconductor package includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first semiconductor substrate, a first bonding structure and a memory cell. The second semiconductor device is stacked over the first semiconductor device. The second semiconductor device includes a second semiconductor substrate, a second bonding structure in a second dielectric layer and a peripheral circuit between the second semiconductor substrate and the second bonding structure. The first bonding structure and the second bonding structure are bonded and disposed between the memory cell and the peripheral circuit, and the memory cell and the peripheral circuit are electrically connected through the first bonding structure and the second bonding structure.