Abstract: A semiconductor structure is provided. The semiconductor structure includes a functional cell region including an n-type functional transistor and a p-type functional transistor. The semiconductor structure also includes a first power transmission cell region including a first cutting feature and a first contact rail in the first cutting feature. The semiconductor structure also includes a first power rail electrically connected to a source terminal of the p-type functional transistor and the first contact rail of the first power transmission cell region. The semiconductor structure also includes a second power transmission cell region adjacent to the first power transmission cell and including a second cutting feature and second contact rail in the second cutting feature. The semiconductor structure also includes an insulating strip extending from the first cutting feature to the second cutting feature in a first direction.

Abstract: A wireless communication method for use in a first wireless network node is disclosed. The method comprises receiving status information indicating at least one missing packet for which a successfully delivery has not been confirmed by a first device, wherein the first device connected to the first wireless network via a second device, and transmitting, to a second wireless network node, the at least one missing packet.

Abstract: Presented are systems and methods for traffic transmission in an integrated access and backhaul (IAB) network. A first network node can send a first message to a second network node. The first message can include information to manage the migration of traffic between a first topology managed by the first network node and a second topology managed by the second network node. A first network node can send a first message to an IAB-node. The first message can include information for re-routing of traffic.

Abstract: A semiconductor device includes a substrate and a transistor. The transistor includes a first channel region overlying the substrate and a source/drain region in contact with the first channel region. The source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region.

Abstract: A semiconductor structure includes a substrate, first channel layers vertically stacked over the substrate in a first region, and second channel layers vertically stacked over the substrate in a second region. The first and second regions have opposite conductivity types. The semiconductor structure also includes a threshold voltage (Vt) modulation layer wrapping around each of the second channel layers in the second region. The first region is free of the Vt modulation layer. The semiconductor structure also includes a gate dielectric layer wrapping around each of the first channel layers and the second channel layers over the Vt modulation layer, and a work function metal layer disposed on the gate dielectric layer and wrapping around each of the first channel layers and the second channel layers.

Abstract: A memory cell includes first and second active regions and first and second gate structures. The first gate structure engages the first and second active regions in forming a first pull-down transistor and a first pull-up transistor, respectively. The second gate structure engages the first and second active regions in forming a second pull-down transistor and a second pull-up transistor, respectively. The memory cell also includes a first source/drain contact via electrically coupled to the first and second pull-down transistors, a second source/drain contact via electrically coupled to the first and second pull-up transistors, a first gate contact electrically coupled to the first gate structure, and a second gate contact electrically coupled to the second gate structure. One of the first and second source/drain contact vias has an area larger than either of the first and second gate contacts in a top view of the memory cell.

Abstract: A method of assessing the brain lymphatic or glymphatic system and the glucose transporter function on blood-cerebrospinal fluid barrier (BCSFB) of a subject using D-glucose or a D-glucose analog. A spatial map is generated of water MR signals that are sensitized to changes in D-glucose or a D-glucose analog in cerebrospinal fluid (CSF) of the subject. The spatial map is observed at one or more time points before, one or more time points during, and one or more time points after, raising the blood level of the D-glucose or a D-glucose analog in the subject CSF. A difference is detected between the MR signals of the spatial map before, during, and after raising the blood level of D-glucose or a D-glucose analog. A physiological parameter associated with the brain lymphatic or glymphatic system and the glucose transporter function on BCSFB of the subject is ascertained based on the detected difference.

Abstract: An elevator interactive terminal and an elevator interactive system. The elevator interactive system of the present invention comprises an elevator interactive terminal, configured with a social communication media module, wherein a user is registered as a first registered user in the social communication media module; and a server coupled to a communication bus of an elevator system, configured with the social communication media module and to register an elevator as the second registered user in the social communication media module, wherein, based on the social communication media module, interactive communication is performed between the first registered user on the elevator interactive terminal corresponding to the user and the second registered user on the server corresponding to the elevator.

Abstract: A current transmission assembly and a current transmission system are provided. The current transmission system includes the current transmission assembly and a circuit board structure. The current transmission assembly includes a pluggable component, at least one conductor component, and at least one electrically connecting component. The pluggable component includes a housing, at least one set of electrically conductive arms, and at least one connecting member. The at least one sets of electrically conductive arms is disposed inside the housing. The at least one conductor component includes an electrical insulator and a wire main body. The electrical insulator encircles the wire main body, so that a first terminal and a second terminal are exposed from the wire main body, and the first terminal is connected to the at least one two connecting member.

Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a substrate having a p-type well or an n-type well, a first base portion over the p-type well, a second base portion over the n-type well, a first plurality of channel members over the first base portion, a second plurality of channel members over the second base portion, an isolation feature disposed between the first base portion and the second base portion, and a deep isolation structure in the substrate disposed below the isolation feature.

Abstract: Described herein are multi-layered windows for use in chemical-mechanical planarization (CMP) systems and CMP processes. The multi-layered windows of the present disclosure include a transparent structural layer and a hydrophilic surfactant applied to at least a portion of at least one surface of the transparent structural layer. Such multi-layered windows may be in the polishing pad, the platen, or both.

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes multiple semiconductor nanostructures over a substrate and two epitaxial structures over the substrate. Each of the semiconductor nanostructures is between the epitaxial structures. The semiconductor device structure also includes a gate stack wrapped around the semiconductor nanostructures, and the gate stack has a gate dielectric layer and a gate electrode. The semiconductor device structure further includes a dielectric stressor structure between the gate stack and the substrate. The gate dielectric layer extends along and beyond first opposite sidewalls of the dielectric stressor structure.

Abstract: A method for assessing risk of chronic kidney disease includes following steps. A reference database is provided. A nucleic acid sample and a biological dataset of a subject are provided. A genetic testing step is performed. A risk score calculating step is performed. A model establishing step is performed, wherein a plurality of reference polygenic risk score data, a plurality of reference clinical data and a plurality of reference genetic marker data of the reference database are trained to achieve a convergence by a machine learning algorithm so as to obtain an analysis model. A data analysis step is performed, wherein a polygenic risk score, a clinical data and a genetic marker data of a subject are analyzed by the analysis model so as to obtain a risk analysis result.

Abstract: Implementations described herein reduce electron-hole pair generation due to silicon dangling bonds in pixel sensors. In some implementations, the silicon dangling bonds in a pixel sensor may be passivated by silicon-fluorine (Si—F) bonding in various portions of the pixel sensor such as a transfer gate contact via or a shallow trench isolation region, among other examples. The silicon-fluorine bonds are formed by fluorine implantation and/or another type of semiconductor processing operation. In some implementations, the silicon-fluorine bonds are formed as part of a cleaning operation using fluorine (F) such that the fluorine may bond with the silicon of the pixel sensor. Additionally, or alternatively, the silicon-fluorine bonds are formed as part of a doping operation in which boron (B) and/or another p-type doping element is used with fluorine such that the fluorine may bond with the silicon of the pixel sensor.

Abstract: Germanium-based sensors are disclosed herein. An exemplary germanium-based sensor includes a germanium photodiode and a junction field effect transistor (JFET) formed from a germanium layer disposed on and/or in a silicon substrate. A doped silicon layer, which can be formed by in-situ doping epitaxially grown silicon, is disposed between the germanium layer and the silicon substrate. In embodiments where the germanium layer is on the silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. The JFET has a doped polysilicon gate, and in some embodiments, a gate diffusion region is disposed in the germanium layer under the doped polysilicon gate. In some embodiments, a pinned photodiode passivation layer is disposed in the germanium layer. In some embodiments, a pair of doped regions in the germanium layer is configured as an e-lens of the germanium-based sensor.

Abstract: A semiconductor image sensor includes a first substrate including a first front side and a first back side, and a second substrate including a second front side and a second back side. The first substrate includes a layer and a first light-sensing element in the layer. The layer includes a first semiconductor material, and the first light-sensing element includes a second semiconductor material. The second substrate is bonded to the first substrate with the second front side facing the first back side.

Abstract: Methods for fabricating a bipolar junction transistor (BJT) are provided. A method includes forming a collector region, forming base regions over the collector region, and forming emitter regions over the base regions. The method further includes forming base dielectric layers over the collector region and on opposite sides of the base regions, forming base conductive layers over the base dielectric layers and on the opposite sides of the base regions, and forming base contacts over the base conductive layers. The top surface of the collector region is coplanar with bottom surfaces of the base regions and bottom surfaces of the base dielectric layers. The base contacts are divided into a first group of base contacts disposed between the base regions and a second group of base contacts disposed between the base regions and the STI region.

Abstract: An array of nanoscale structures over photodiodes of a pixel array improves quantum efficiency (QE) for shorter wavelengths of light, such as green light and blue light. The nanoscale structures may be used without high absorption (HA) structures (e.g., when the pixel array is configured only for visible light) or may at least partially surround HA structures (e.g., when the pixel array is configured both for visible light and near infrared light). Additionally, the array of nanoscale structures may be formed using photolithography such that the nanoscale structures are approximately spaced at regular intervals. Therefore, QE for the pixel array is improved more than if the array of nanoscale structures were to be formed using a random (or quasi-random) process.

Abstract: Semiconductor devices and their manufacturing methods are disclosed herein, and more particularly to semiconductor devices including a transistor having gate all around (GAA) transistor structures and manufacturing methods thereof. The methods described herein allow for complex shapes (e.g., “L-shaped”) to be etched into a multi-layered stack to form fins used in the formation of active regions of the GAA nanostructure transistor structures. In some embodiments, the active regions may be formed with a first channel width and a first source/drain region having a first width and a second channel width and a second source/drain region having a second width that is less than the first width.

Abstract: A device includes a first channel layer over a semiconductor substrate, a second channel layer over the first channel layer, and a third channel layer over the second channel layer. The channel layers each connects a first and a second source/drain along a first direction. The device also includes a first gate portion between the first and second channel layers; a second gate portion between the second and third channel layers; a first inner spacer between the first and second channel layers and between the first gate portion and the first source/drain; and a second inner spacer between the second and third channel layers and between the second gate portion and the first source/drain. The first and second gate portions have substantially the same gate lengths along the first direction. The first inner spacer has a width along the first direction that is greater than the second inner spacer has.