Patents by Inventor Lin Chen

Lin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240071837
    Abstract: A wafer metrology system having a continuous dynamic sampling scheme configured to optimize a sampling rate for AVI of process wafers in an IC fabrication flow based on acceptable quality levels. For a stable process, the process wafers may be sampled at a lower rate without negatively affecting quality control.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Inventors: Bin Liu, Lin Lin, Yu Chen Li, Si Si Xie, Zhi Yun Liu, Bo Jiang
  • Publication number: 20240066326
    Abstract: A neutron capture therapy system is provided, including a neutron generating device and a beam shaping assembly. The neutron capture therapy system further includes a concrete wall forming a space for accommodating the neutron generating device and the beam shaping assembly and shielding radiations generated by the neutron generating device and the beam shaping assembly. A support module is disposed in the concrete wall, the support module is capable of supporting the beam shaping assembly and is used to adjust the position of the beam shaping assembly, and the support module includes concrete and a reinforcing portion at least partially disposed in the concrete. The neutron capture therapy system designs a locally adjustable support for the beam shaping assembly, so that the beam shaping assembly can meet the precision requirement, improve the beam quality, and meet an assembly tolerance of the target.
    Type: Application
    Filed: October 18, 2023
    Publication date: February 29, 2024
    Inventors: Tao JIANG, Wei-lin CHEN
  • Patent number: 11915311
    Abstract: A method, apparatus, and server for generating a user score based on social networking information is provided. In the disclosed method, by processing circuitry of an information processing apparatus, default annotation information of a plurality of sampled users, an ith user score and an ith relative user score for each of the sampled users are obtained. A user score model is trained according to the ith user score of the respective sampled user, the ith relative user score of the respective sampled user, and the default annotation information of the respective sampled user. An (i+1)th user score of the respective sampled user is subsequently calculated and a trained user score model, for each of the sampled users, is obtained when the (i+1)th user score for the respective sampled user satisfies a training termination condition, The method provides a solution to evaluate the user score for a use when personal information of the user is missing or incorrect.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: February 27, 2024
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Peixuan Chen, Qian Chen, Lin Li, Sanping Wu, Weiliang Zhuang
  • Patent number: 11912433
    Abstract: A dual-filter-based transfer alignment method under dynamic deformation. A dynamic deformation angle generated under dynamic deformation and a coupling angle between dynamic deformation and body motion will reduce the accuracy of transfer alignment; and a transfer alignment filter is divided into two parts, the first part estimates a bending deformation angle and the coupling angle, and uses an attitude matching method, and the second part estimates a dynamic lever arm, and uses a “speed plus angular speed” matching method.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: February 27, 2024
    Assignee: SOUTHEAST UNIVERSITY
    Inventors: Xiyuan Chen, Ping Yang, Lin Fang, Junwei Wang
  • Patent number: 11917422
    Abstract: An information handling system executing an intelligent throughput performance analysis and issue detection system may comprise a network interface device to establish a wireless link with a wireless network and a processor to execute a neural network trained to predict wireless link throughput values based on controlled connectivity testing metrics gathered in a controlled laboratory from tested information handling systems. The processor may gather measured throughput of the wireless link and operational connectivity metrics for the information handling system that describe antenna positional information, antenna adaptation controller parameters, signal strength measurements, and wireless link performance metrics. The neural network may output, based on the gathered operational connectivity metrics a predicted throughput value that differs from the measured throughput by a maximum tolerance.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: February 27, 2024
    Assignee: Dell Products, LP
    Inventors: Wei-Chia Huang, Chuang-Yueh Chen, YungShun Lin, Alan Eric Sicher, Lars Fredrik Proejts
  • Patent number: 11917452
    Abstract: Provided are an information transmission method and device. The method includes that: an Integrated Access and Backhaul Links (IAB) node transmits link information to a second IAB node, wherein the second IAB node is an IAB child node or an IAB parent node or an IAB donor. Also provided are an electronic device and a storage medium.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: February 27, 2024
    Assignee: ZTE CORPORATION
    Inventors: Ying Huang, Lin Chen
  • Publication number: 20240059836
    Abstract: A polyphenylene ether bismaleimide resin is provided. The polyphenylene ether bismaleimide resin (PPE-BMI) is formed from a modified polyphenylene ether diamine and a maleic anhydride by a condensation polymerization. The modified polyphenylene ether diamine is formed by reacting a phenol-based compound with a polyphenylene ether.
    Type: Application
    Filed: September 2, 2022
    Publication date: February 22, 2024
    Applicant: NAN YA PLASTICS CORPORATION
    Inventors: Te-Chao Liao, Wen-Hua Lu, Chi-Lin Chen
  • Publication number: 20240064950
    Abstract: A semiconductor device includes a first source/drain feature on a front side of a substrate. The device includes a first backside metal line under the first source/drain feature and extending lengthwise along a first direction. The device includes a first backside via disposed between the first source/drain feature and the first backside metal line. The first backside metal line is a first bit line of a first static random access memory (SRAM) cell and is connected to the first source/drain feature through the first backside via. The first backside metal line includes a first portion and a second portion each extending widthwise along a second direction perpendicular to the first direction, the first portion is wider than the second portion, and the first portion partially lands on the first backside via. The first and the second portions are substantially aligned on one side along the first direction.
    Type: Application
    Filed: August 18, 2022
    Publication date: February 22, 2024
    Inventors: Jui-Lin Chen, Kian-Long Lim, Feng-Ming Chang, Yi-Feng Ting, Hsin-Wen Su, Lien-Jung Hung, Ping-Wei Wang
  • Publication number: 20240063065
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming first, second and third fin structures over a substrate, forming a first dielectric material along a first trench between the first fin structure and the second fin structure and along a second trench between the second fin structure and the third fin structure, removing a first portion of the first dielectric material along the second trench while leaving a second portion of the first dielectric material along the first trench as a dielectric liner, depositing a second dielectric material over the dielectric liner and filling the first trench and the second trench, and etching back the second dielectric material until the dielectric liner is exposed. A first portion of the second dielectric material remaining in the first trench forms a dielectric wall.
    Type: Application
    Filed: August 17, 2022
    Publication date: February 22, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Rong LIN, Kuo-Cheng CHIANG, Shi-Ning JU, Guan-Lin CHEN, Chih-Hao WANG
  • Publication number: 20240064715
    Abstract: A method of wireless communication is described. The method of wireless communication comprises receiving, by a first node of an integrated access and backhaul (IAB) network, resource information that includes resource availability information and/or resource configuration information; and transmitting, by the first node, the resource information to a second node.
    Type: Application
    Filed: November 1, 2023
    Publication date: February 22, 2024
    Inventors: Ying HUANG, Lin CHEN
  • Publication number: 20240059093
    Abstract: The invention refers to a 3D card comprising a foldable base card (1) having an inner side and an outer side, said base card (1) comprising two sections (2, 3) reversibly transferable along a fold (17) from a folded closed state to an unfolded opened state, and a foldable base structure (6, 6?) reversibly transferable from a flat compressed state to a three-dimensional expanded state, and with a foldable FIG. 10) reversibly transferable from a flat compressed state to a three-dimensional expanded state, and wherein the foldable base structure (6, 6?) is formed of a plurality of base elements (I, II, III, IV) and is fixed to the inner side of the foldable base card (1) via first fixing means (7, 7?, 8, 8?), and wherein the foldable FIG.
    Type: Application
    Filed: August 17, 2023
    Publication date: February 22, 2024
    Inventor: Jen-Lin Chen
  • Publication number: 20240062049
    Abstract: A processor implemented method including iteratively training a model through repeated training operations, including calculating a respective sensitivity of each layer of plural layers included in the model, the model including a machine-learning model, calculating a first maintenance probability for a t-th repeated training of the model, calculating a respective maintenance probability of each of the plural layers of the model based on the respective sensitivity of each of the plural layers and based on the first maintenance probability for the t-th repeated training of the model, and performing the t-th repeated training of the model including training selected one or more maintenance layers, of the plural layers of the model, whose respective maintenance probabilities satisfy a first predetermined maintenance condition.
    Type: Application
    Filed: July 20, 2023
    Publication date: February 22, 2024
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yujie ZENG, Wenlong HE, Lin CHEN, Ihor VASYLTSOV
  • Publication number: 20240063126
    Abstract: A semiconductor device structure and methods of forming the same are described. In some embodiments, the structure includes a device and a first dielectric layer disposed over the device. An airgap is located in the first dielectric layer. The structure further includes a conductive feature disposed in the first dielectric layer, and the first dielectric layer includes a first portion disposed between the airgap and a first side of the conductive feature and a second portion disposed adjacent a second side of the conductive feature opposite the first side. The first portion has a first nitrogen concentration, and the second portion has a second nitrogen concentration substantially less than the first nitrogen concentration.
    Type: Application
    Filed: August 17, 2022
    Publication date: February 22, 2024
    Inventors: Lin-Chen Lu, Tsung-Han Tsai
  • Publication number: 20240064952
    Abstract: A semiconductor memory device includes a first dielectric wall, a second dielectric wall, first channel portions, second channel portions, an isolation wall, and a dielectric feature. The second dielectric wall is spaced apart from the first dielectric wall in a first direction. The first channel portions are disposed on a side of the first dielectric wall and are spaced apart from each other in a second direction transverse to the first direction. The second channel portions are disposed on a side of the second dielectric wall and are spaced apart from each other in the second direction. The isolation wall is located between the first dielectric wall and the second dielectric wall. The dielectric feature is disposed to separate the first dielectric wall and the isolation wall, and is disposed on the other side of the first dielectric wall opposite to the first channel portions in the first direction.
    Type: Application
    Filed: August 22, 2022
    Publication date: February 22, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bo-Rong LIN, Kuo-Cheng CHIANG, Shi-Ning JU, Guan-Lin CHEN, Chih-Hao WANG
  • Patent number: 11908900
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material. The second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor. A passivation layer is disposed on the second semiconductor material. The passivation layer includes the first semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yin-Kai Liao, Sin-Yi Jiang, Hsiang-Lin Chen, Yi-Shin Chu, Po-Chun Liu, Kuan-Chieh Huang, Jyh-Ming Hung, Jen-Cheng Liu
  • Publication number: 20240055502
    Abstract: A method of forming a semiconductor device includes etching trenches in a substrate to form semiconductor fins, filling a first one of the trenches with a dielectric fin, forming an insulation material in a second one of the trenches, performing a first recessing process to recess the insulation material and form a gap on a top of the dielectric fin, filling the gap with a dielectric cap, and forming a gate stack across the semiconductor fins and the dielectric fin.
    Type: Application
    Filed: August 12, 2022
    Publication date: February 15, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Guan-Lin CHEN, Kuo-Cheng CHIANG, Shi Ning JU, Jung-Chien CHENG, Chih-Hao WANG
  • Publication number: 20240052470
    Abstract: Disclosed is a non-quenched and tempered round steel with high strength, high toughness and easy cutting, comprising the following chemical elements in percentage by mass: C: 0.36-0.45%, Si: 0.20-0.70%, Mn: 1.25-1.85%, Cr: 0.15-0.55%, Ni: 0.10-0.25%, Mo: 0.10-0.25%, Al: 0.02-0.05%, Nb: 0.001-0.040%, V: 0.10-0.25%, S: 0.02-0.06%, and the balance being Fe and inevitable impurities. Also disclosed is a method for manufacturing the non-quenched and tempered round steel, comprising the steps of: S1: smelting and casting; S2: heating; S3: forging or rolling; and S4: finishing. The non-quenched and tempered round steel with high strength, high toughness and easy cutting described above has high strength, good impact toughness, elongation and cross-sectional shrinkage, and has good cutting performance and fatigue resistance, and can be used in situations requiring a high-strength steel material, such as automobiles and engineering machinery.
    Type: Application
    Filed: January 12, 2022
    Publication date: February 15, 2024
    Inventors: Jiaqiang GAO, Sixin ZHAO, Zongze HUANG, Lin CHEN
  • Publication number: 20240055478
    Abstract: A semiconductor device structure and a formation method are provided. The method includes forming a first fin structure and a second fin structure over a substrate. The method also includes forming a first metal gate stack wrapped around and extending across the first fin structure and the second fin structure. The method further includes forming a second metal gate stack wrapped around and extending across the first fin structure and the second fin structure. In addition, the method includes forming a protective structure extending into the first gate stack and forming a dielectric structure extending into the protective structure and the second metal gate stack. A portion of the protective structure is between the dielectric structure and the metal gate stack.
    Type: Application
    Filed: August 12, 2022
    Publication date: February 15, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Chien CHENG, Kuo-Cheng CHIANG, Shi-Ning JU, Guan-Lin CHEN, Chih-Hao WANG
  • Patent number: 11900848
    Abstract: Disclosed in the present application are a color gamut mapping method, a color gamut mapping assembly, and a display device. The method includes: obtaining a first connection line between a white point and an original point of the original color gamut; obtaining a first mapping point in a target color gamut of an intersection point of the first connection line and the original color gamut; obtaining a second connection line between a reference point in the original color gamut and the first mapping point; obtaining color coordinates of a second mapping point of the original point in the target color gamut; obtaining a luminance value of the second mapping point according to the original point and the white point; and obtaining grayscale values of the second mapping point according to the color coordinates and the luminance value of the second mapping point.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: February 13, 2024
    Assignee: SHENZHEN TCL DIGITAL TECHNOLOGY LTD.
    Inventors: Lin Chen, Daxue Xia, Renli Xie
  • Patent number: 11900846
    Abstract: The present application provides a chrominance visual angle correction method for a display, and an intelligent terminal and a storage medium. The method comprises: acquiring brightness data of different primary colors varying with the gray scale at a vertical visual angle and a squint visual angle, and generating a search database; splitting, according to the search database and a preset rule, a pixel gray scale of the display into a plurality of high and low gray scale combinations composed of high gray scales and low gray scales; calculating a scale of brightness of the plurality of high and low gray scale combinations, and acquiring a scale of brightness of high and low gray scale combination closest to a scale of vertical vision brightness as a primary color pixel gray scale.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: February 13, 2024
    Assignee: SHENZHEN TCL NEW TECHNOLOGY CO., LTD.
    Inventors: Daxue Xia, Lin Chen, Renli Xie