Patents by Inventor Lin Chen

Lin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250048763
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. A photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. The passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer.
    Type: Application
    Filed: October 21, 2024
    Publication date: February 6, 2025
    Inventors: Hsiang-Lin Chen, Yi-Shin Chu, Yin-Kai Liao, Sin-Yi Jiang, Kuan-Chieh Huang, Jhy-Jyi Sze
  • Publication number: 20250048166
    Abstract: A wireless communication method for use in a first wireless terminal is disclosed. The method comprises receiving, from a first wireless network node, a sidelink (SL) measurement configuration associated with a user-to-user relay for the first wireless terminal and a second wireless terminal, and transmitting, to the first wireless network node, a measurement report based on the measurement configuration.
    Type: Application
    Filed: October 25, 2024
    Publication date: February 6, 2025
    Applicant: ZTE CORPORATION
    Inventors: Mengzhen WANG, Lin CHEN, Wanfu XU, Weiqiang DU, Tao QI
  • Publication number: 20250048686
    Abstract: The present disclosure provides an integrated circuit (IC) structure that includes a semiconductor substrate having a frontside and a backside; a shallow trench isolation (STI) structure formed in the semiconductor substrate and defining an active region, wherein the STI structure includes a STI bottom surface, wherein the semiconductor substrate includes a substrate bottom surface, and wherein the STI bottom surface and the substrate bottom surface are coplanar; a field-effect transistor (FET) over the active region and formed on the frontside of the semiconductor substrate; and a backside dielectric layer disposed on the substrate bottom surface and the STI bottom surface.
    Type: Application
    Filed: January 11, 2024
    Publication date: February 6, 2025
    Inventors: Ping-Wei Wang, Gu-Huan Li, Jui-Lin Chen
  • Publication number: 20250048613
    Abstract: The present disclosure provides an IC structure that includes a semiconductor substrate having a SRAM region, an input/output and peripheral (IOP) region, and an edge region spanning tween the SRAM region and the IOP region; a STI structure formed on the semiconductor substrate and defining active regions; a SRAM cell formed within the SRAM region; and a backside dielectric layer disposed on a backside of the semiconductor substrate and landing on a bottom surface of the STI structure. The active regions are longitudinally oriented along a first direction; gates are formed on the semiconductor substrate and are evenly distributed with a pitch P along the first direction; the SRAM cell spans a first dimension Ds along the first direction; the edge region spans a second dimension De along the first direction; and a ratio De/Ds equals to 2 or is less than 2.
    Type: Application
    Filed: January 12, 2024
    Publication date: February 6, 2025
    Inventors: Jui-Lin Chen, Feng-Ming Chang, Ping-Wei Wang, Yu-Bey Wu
  • Publication number: 20250048612
    Abstract: An integrated circuit (IC) device has a memory region in which a plurality of memory cells is implemented. Each of the memory cells has a first dimension in a first horizontal direction. The IC device includes an edge region bordering the memory cell region in the first horizontal direction. The edge region has a second dimension in the first horizontal direction. The second dimension is less than or equal to about 4 times the first dimension. The IC device is formed by revising a first IC layout to generate a second IC layout. The second IC layout is generated by shrinking a dimension of the edge region in the first horizontal direction.
    Type: Application
    Filed: January 4, 2024
    Publication date: February 6, 2025
    Inventors: Jui-Lin Chen, Feng-Ming Chang, Ping-Wei Wang, Yu-Bey Wu, Chih-Ching Wang
  • Publication number: 20250046961
    Abstract: A lithium battery cell includes an upper cover module, a first battery electrode group, a second battery electrode group, and a plurality of first electrode connection straps. The first electrode connection straps are stacked together. A first end of the first electrode connection straps is welded to a first tab, a second end of the first electrode connection straps is welded to a second tab, and a middle part of the first electrode connection straps is welded to a first electrode terminal. An even number of first bending parts are formed between the middle part and the first end, and an even number of second bending parts are formed between the middle part and the second end, and the first bending parts and the second bending parts are symmetrical to each other. A lithium battery cell manufacturing method is also disclosed therein.
    Type: Application
    Filed: October 25, 2024
    Publication date: February 6, 2025
    Inventors: Cheng-Huang CHEN, Yi-Hsiang CHAN, Shu-Lin CHEN, Wei-En HSU
  • Patent number: 12218160
    Abstract: A pixel sensor may include a layer stack to reduce and/or block the effects of plasma and etching on a photodiode and/or other lower-level layers. The layer stack may include a first oxide layer, a layer having a band gap that is approximately less than 8.8 electron-Volts (eV), and a second oxide layer. The layer stack may reduce and/or prevent the penetration and absorption of ultraviolet photons resulting from the plasma and etching processes, which may otherwise cause the formation of electron-hole pairs in the substrate in which the photodiode is included.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Lin Chen, Ching-Chung Su, Chun-Hao Chou, Kuo-Cheng Lee
  • Publication number: 20250036953
    Abstract: In some example embodiments, there may be provided a method that includes receiving, at a machine learning model, an input for a task of the machine learning model, wherein the machine learning model comprises a plurality of residual blocks augmented with a plurality of augmented weight blocks that sample intermediate features from the plurality of residual blocks; applying the input to the machine learning model to perform the task, wherein the applying comprises applying the plurality of intermediate features, which are obtained from the plurality of residual blocks, to the plurality of augmented weight blocks to form a plurality of intermediate outputs; and generating an output of the machine learning model, wherein the output is generated using at least on a combination of the plurality of intermediate outputs. Related systems, methods, and articles of manufacture are also disclosed.
    Type: Application
    Filed: December 5, 2022
    Publication date: January 30, 2025
    Inventors: Harinath Garudadri, Kuan-Lin Chen, Bhaskar D. Rao, Ching-Hua Lee
  • Publication number: 20250040235
    Abstract: A method for manufacturing an integrated circuit device is provided. The method includes depositing an epitaxial stack comprising alternative first and second semiconductor layers over a semiconductor substrate; patterning the epitaxial stack to form first and second semiconductor fins; removing the first semiconductor layers in the first and second semiconductor fins, while leaving a first set of the second semiconductor layers in the first semiconductor fin and a second set of the second semiconductor layers in the second semiconductor fin; forming a gate dielectric layer around the first and second sets of the second semiconductor layers; depositing a gate metal layer over the gate dielectric layer; etching a recess in the gate metal layer and between the first and second sets of the second semiconductor layers, wherein the gate metal layer has a first portion below the recess; and forming a dielectric feature in the recess.
    Type: Application
    Filed: July 25, 2023
    Publication date: January 30, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Guan-Lin Chen, Kuo-Cheng Chiang, Jung-Chien Cheng, Shi Ning Ju, Chih-Hao Wang
  • Publication number: 20250037273
    Abstract: A method of estimating a distance in an endoscopic image is implemented by an endoscopic system. The method includes steps of: irradiating a lesion of a subject and obtaining an image of the lesion and a scale of the endoscopic system as a to-be-analyzed image while the lesion is being irradiated and the scale is placed adjacent to the lesion; using a lesion-contour prediction model to generate a prediction result that indicates a contour of the lesion; displaying the prediction result; generating two selected points on the contour of the lesion; and estimating, based on the scale in the to-be-analyzed image, an actual distance between the two selected points.
    Type: Application
    Filed: May 17, 2024
    Publication date: January 30, 2025
    Inventors: Po-Wen LU, Xiu-Zhi CHEN, Yen-Lin CHEN
  • Patent number: 12211910
    Abstract: Bipolar junction transistor (BJT) structures are provided. A BJT structure includes a semiconductor substrate, a collector region formed in the semiconductor substrate, a base region formed over the collector region, an emitter region formed over the collector region, a ring-shaped shallow trench isolation (STI) region formed in the collector region, and a base dielectric layer formed over the collector region and on opposite sides of the base region. The base dielectric layer is surrounded by an inner side wall of the ring-shaped STI region.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuan-Jung Chen, Chun-Ming Lin, Tsung-Lin Lee, Shiuan-Jeng Lin, Hung-Lin Chen
  • Patent number: 12207961
    Abstract: The present disclosure provides a method for correcting a resting blood flow velocity on the basis of an interval time between angiogram images, comprising: acquiring, in an angiography state, an average blood flow velocity Vh from a coronary artery inlet to a distal end of a coronary artery stenosis (S100); acquiring a time difference ?t between start times of two adjacent bolus injections of contrast agent (S200); obtaining a correction coefficient K according to the time difference ?t (S300); obtaining a resting blood flow velocity Vj according to the correction coefficient K and the average blood flow velocity Vh (S400), as well as an apparatus configured for implementing the above method. The disclosure obtains the resting blood flow velocity Vj according to the correction coefficient K and the average blood flow velocity Vh.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: January 28, 2025
    Assignee: SUZHOU RAINMED MEDICAL TECHNOLOGY CO., LTD.
    Inventors: Guangzhi Liu, Zhiyuan Wang, Wei Dai, Lin Chen
  • Patent number: 12210753
    Abstract: Systems, apparatus and methods are provided for determining an optimal performance profile and a predicted temperature. A method may include receiving a command from a host. The command may contain a logical block address (LBA) for data stored in a data storage system, a length for a data size associated with the command, and a timestamp associated with the command. The method may further include obtaining LBA information, the timestamp, the data size from the command, providing the LBA information, the timestamp, the data size, along with temperature readings, and a performance profile as inputs to a machine learning model, determining an optimal performance profile and a predicted temperature using the machine learning model and configuring a storage controller with settings of the optimal performance profile.
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: January 28, 2025
    Assignee: Innogrit Technologies Co., Ltd.
    Inventors: Gang Zhao, Lin Chen
  • Patent number: 12213297
    Abstract: A method comprises forming a first fin including alternating first channel layers and first sacrificial layers and a second fin including alternating second channel layers and second sacrificial layers, forming a capping layer over the first and the second fin, forming a dummy gate stack over the capping layer, forming source/drain (S/D) features in the first and the second fin, removing the dummy gate stack to form a gate trench, removing the first sacrificial layers and the capping layer over the first fin to form first gaps, removing the capping layer over the second fin and portions of the second sacrificial layers to from second gaps, where remaining portions of the second sacrificial layers and the capping layers form a threshold voltage (Vt) modulation layer, and forming a metal gate stack in the gate trench, the first gaps, and the second gaps.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Hao Lin, Chih-Hsiang Huang, Shang-Rong Li, Chih-Chuan Yang, Jui-Lin Chen, Ming-Shuan Li
  • Publication number: 20250031387
    Abstract: A method of forming a capacitor structure includes a number of operations. A single carbon film is deposited over tops of bottom electrode plates. The single carbon film is patterned. The bottom electrode plates are etched based on the single carbon film after the single carbon film is patterned. The single carbon film is removed after the bottom electrode plates are etched. A dielectric layer is formed over the bottom electrode plates. A plurality of top electrode plates is formed over the dielectric layer and aligned with the bottom electrode plates.
    Type: Application
    Filed: July 21, 2023
    Publication date: January 23, 2025
    Inventor: Hui-Lin CHEN
  • Publication number: 20250026440
    Abstract: A power module of an electric assisted bicycle is disclosed and includes a pedal shaft, a housing, a motor, a reducer and a gear-plate output shaft and a sensing component. The housing includes a partition portion extended along a radial direction to divide an inner space of the housing into a motor accommodation portion and a reducer accommodation portion for accommodating the motor and the reducer, respectively. A stator of the motor and a fixed gear are respectively fixed to a first side and a second side, which are two opposite sides of the partition portion. A reducer input shaft includes two ends connected to the motor and the reducer, respectively, and an input-shaft main part disposed therebetween is connected to a third side of the partition portion. With the connection configuration of the three sides of the partition portion, the space utilization of the entire power module is optimized.
    Type: Application
    Filed: February 5, 2024
    Publication date: January 23, 2025
    Inventors: Chi-Wen Chung, Ming-Li Tsao, Chien-Ping Huang, Chun-Lin Chen
  • Publication number: 20250030515
    Abstract: Provided are a signal transmission method and apparatus, a device, and a computer storage medium. A method for sending a measurement reference signal includes: determining parameter information of the measurement reference signal according to received signaling information and/or a pre-negotiated parameter determination rule; and sending the measurement reference signal according to the determined parameter information.
    Type: Application
    Filed: September 30, 2024
    Publication date: January 23, 2025
    Inventors: Shujuan ZHANG, Chuangxin JIANG, Feng BI, Xing LIU, Lin CHEN
  • Publication number: 20250027363
    Abstract: A motorized venetian blind includes a first lifting electric machine, a second lifting electric machine and a tilting electric machine for respectively control a front pull cord, a rear pull cord and a ladder cord. When a front warp and a rear warp of the ladder cord are controlled by the tilting electric machine to move downwardly and upwardly respectively to tilt the slats to the closed position, one of the pull cords on the same side as the upwardly-moving warp is controlled by the first lifting electric machine or the second lifting electric machine to move upwardly along with the upwardly-moving warp. Therefore, the synchronization of the pull cords and the ladder cord is improved, whereby closure between the slats is enhanced, and the bottom rail can be fully tilted to be mostly vertical, partially overlapping the neighboring slat for preventing light leakage.
    Type: Application
    Filed: July 9, 2024
    Publication date: January 23, 2025
    Applicant: Nien Made Enterprise Co., Ltd.
    Inventors: Lin Chen, Jian Zeng
  • Patent number: 12202656
    Abstract: The invention relates to a container for accommodating one or more objects, with the container having a main body and a lid, with the main body having a bottom as well as side walls forming a border structure pointing towards the lid, with the container having a connecting edge via which the main body and lid are pivotably connected to one another, wherein the container is provided with a unfoldable figure which is reversibly transferable from a compressed flat state to a three-dimensional expanded state, and means for producing visual and/or acoustic effects, wherein the container has a foldable insert sheet that has at least five sections arranged one behind the other in the longitudinal direction, the 1st section covering the inner side of the lid, the 2nd and 5th sections, laid one on top of the other, being placed into the main body and the 3rd and 4th sections, laid one on top of the other, resting against the inside of the side wall opposite the connecting edge, wherein between the bottom and the 2nd a
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: January 21, 2025
    Assignee: JAST Gifts Shenzhen Company Limited
    Inventor: Jen-Lin Chen
  • Patent number: 12206809
    Abstract: An easily disassembled lens module in a terminal device includes a lens assembly, a circuit board, and a structural member. The circuit board includes a first portion, a second portion, and a third portion which are connected in sequence. The first portion is connected to the lens assembly, the second portion and the third portion protrude from the lens assembly. The structural member includes a connecting portion fixed on the third portion and at least one pulling portion protruding from the third portion. After installation in the terminal device, the lens assembly can be disassembled by using the at least one pulling portion to pull on the structural member so that the lens assembly can be disassembled without using tools and without causing damage.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: January 21, 2025
    Assignee: TRIPLE WIN TECHNOLOGY(SHENZHEN) CO. LTD.
    Inventors: Ying-Lin Chen, Hui-Hui Shangguan, Hu Zhu, Xiao-Fei Wang, Zheng-Zhi Lun