Abstract: This disclosure provides for robust isolation across the SOI structure. In contrast to forming a charge trap layer in specific areas on the structure, a charge trap layer may be built across the insulating/substrate interface. The charge trap layer may be an implantation layer formed throughout and below the insulation layer. Devices built on this SOI structure have reduced cross-talk between the devices. Due to the uniform structure, isolation is robust across the structure and not confined to certain areas. Additionally, deep trench implantation is not required to form the structure, eliminating cost. The semiconductor-on-insulator substrate may include an active silicon layer over an oxide layer. The oxide layer may be over a charge trap layer. The charge trap layer may be over a silicon substrate.

Abstract: A supporting device is provided and includes: a base; an upright column disposed on the base; a lifting module disposed on the upright column; a constant force arm unit including: a first rotating member rotatably disposed on the upright column and defining a constant first effective force arm; and a first wire wound on the first rotating member; a variable force arm unit including: a second rotating member linked with the first rotating member and defining a variable second effective force arm; and a second wire wound on the second rotating member; and an elastic force module connected to the first wire; where the torques respectively generated in the first wire and the second wire are balanced with each other.

Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.

Abstract: Disclosed is a three-dimensional integrated system for DRAM chips and a fabrication method thereof. A plurality of trench structures are etched on the front and back of a silicon wafer; then, a TSV structure is etched between the two upper and lower trenches opposite to each other for electrical connection; then, DRAM chips are placed in the trenches, and copper-copper bonding is used to make the chips electrically connected to the TSV structure in a vertical direction; finally, redistribution is done to make the chips in a horizontal direction electrically connected. The invention can make full use of silicon materials, and can avoid problems such as warpage and deformation of an interposer. In addition, placing the chips in the trenches will not increase the overall package thickness, while protecting the chips from external impact.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a dielectric feature comprising a first dielectric layer and a second dielectric layer, the first dielectric layer has a first sidewall and a second sidewall opposing the first sidewall, and the second dielectric layer is in contact with at least a portion of the first sidewall and at least a portion of the second sidewall. The structure also includes a first semiconductor layer adjacent the first sidewall, wherein the first semiconductor layer is in contact with the second dielectric layer. The structure further includes a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, wherein the first gate electrode layer has a surface facing the second dielectric layer, and the surface extends over a plane defined by an interface between the second dielectric layer and the first semiconductor layer.

Abstract: An information processing method, an interconnection device, and a computer-readable storage medium are provided. The interconnection device includes a request processing module configured for: receiving a data access request from at least one processor, wherein the data access request comprises a merge bit, a multicast group identifier (MGID), and a multicast transaction identifier (MTID); determining whether the data access request is a multicast request; determining whether the interconnection device receives other multicast requests if it is determined that the data access request is a multicast request based on the MGID, the MTID, and a static routing policy of a multicast group; and obtaining the other multicast requests if it is determined that the interconnection device receives the other multicast requests, merging the multicast request with the other multicast requests into a merged request, and forwarding the merged request to a next-hop device of the interconnection device.

Abstract: An integrated circuit includes a first nanosheet transistor and a second nanosheet transistor on a substrate. The first and second nanosheet each include gate electrodes. A gate isolation structure extends from a backside of the substrate between the gate electrodes. The gate isolation structure physically and electrically isolates the first and second gate electrodes from each other.

Abstract: Germanium-based sensors are disclosed herein. An exemplary germanium-based sensor includes a germanium photodiode and a junction field effect transistor (JFET) formed from a germanium layer disposed on and/or in a silicon substrate. A doped silicon layer, which can be formed by in-situ doping epitaxially grown silicon, is disposed between the germanium layer and the silicon substrate. In embodiments where the germanium layer is on the silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. The JFET has a doped polysilicon gate, and in some embodiments, a gate diffusion region is disposed in the germanium layer under the doped polysilicon gate. In some embodiments, a pinned photodiode passivation layer is disposed in the germanium layer. In some embodiments, a pair of doped regions in the germanium layer is configured as an e-lens of the germanium-based sensor.

Abstract: A power semiconductor package comprises a lead frame, a semiconductor chip, and a molding encapsulation. The lead frame comprises an elevated section comprising a source section; a drain section; and a plurality of leads. The semiconductor chip includes a metal-oxide-semiconductor field-effect transistor (MOSFET) disposed over the lead frame. The semiconductor chip comprises a source electrode, a drain electrode, and a gate electrode. The source electrode of the semiconductor chip is electrically and mechanically connected to the source section of the elevated section of the lead frame. The semiconductor chip is served as a low side field-effect transistor as a flipped-chip connected to a heat sink by a first thermal interface material. A high side field-effect transistor is connected to the heat sink by a second thermal interface material. The low side field-effect transistor and the high side field-effect transistor are mounted on a printed circuit board.

Abstract: A circuit board assembly in a camera module for blocking unwanted light when images are captured includes a circuit board, a sensor, and an optical blocking body connecting the circuit board and the sensor. The circuit board includes a base board and a photomask. The photomask is arranged on a surface of the base board, the base board includes conductive circuit layers and dielectric layers, the conductive circuit layers and the dielectric layers are alternately arranged, the sensor being electronically connected to the conductive layers. The optical blocking body, the photomask, and the dielectric layers block ambient light entering the camera module other than through the lens assembly of the camera module.

Abstract: Apparatus and methods are provided for determining AR filter coefficient and numbers of synchronization. In one novel aspect, the AR filter coefficient and times of synchronization are determined based on the temperatures of the oscillator. In one embodiment, the UE determines a temperature drift rate by collecting sets of temperatures before and after the UE in the sleep mode of the CDRX, generates one or more threshold look-up tables and performs an optimization selection based on the temperature drift rate and the one or more threshold of look-up tables, wherein the optimization selection comprising selecting an alpha coefficient and a number of subframes for synchronization. In another embodiment, the optimization selection is further determined based on a subcarrier spacing, and a channel type of being a static channel type and a fading channel type. The UE further performs an on-the-fly oscillator S-curve calibration based on the set of temperatures.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. A photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. The passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer.

Abstract: Systems and methods for sharing a resource pool in wireless sidelink communications are disclosed herein. In one embodiment, a method performed by a first node is disclosed. The method comprises: sensing on a resource pool shared by a group of nodes for sidelink communications; and transmitting a report related to the shared resource pool to a second node, wherein the second node is outside the group of nodes and schedules sidelink communication resources for at least one node of the group of nodes based on the report.

Abstract: A method and system or device such as a hearing aid are provided for processing audio signals. In accordance with the method, an audio signal is received and divided into a plurality of frequency sub-bands. For each of the frequency sub-band signals, the signal is further divided into overlapping temporal frames. Each of the temporal frames are windowed. Frequency warping is performed on each of the windowed frames. Overlap-and-add is performed on the frequency warped frames. The frequency warped sub-bands are combined into a full band to provide a frequency warped signal.

Abstract: An image display device is provided. The image display device includes a display unit and a backlight module. The display unit is used for displaying pictures in an image frame cycle. The backlight module includes a plurality of light sources of different colors. The image frame cycle is divided into a first interval, a second interval and a third interval in sequence, and the second interval is adjacent to the first interval. The backlight module provides a white light source with a first intensity in the first interval and provides a white light source with a second intensity in the second interval, and the second intensity is smaller than the first intensity. The backlight module is turned off in the third interval.

Abstract: The invention relates to a foldable greeting card having an outer side and an inner side and a number of electronic and electrical components, the card (1) being provided in a foldable manner, comprising a fold at one point which divides the card preferably into two parts (2, 3) of equal size, thus having two halves which can be folded congruently on top of one another, at least one part (2) being provided at least partially in two layers with an inner and an outer layer, and at least some of the electronic and electrical components comprising light and acoustic elements (5, 9) for generating light and sound effects, a switch (8) for activating the light and acoustic elements (5, 9), a circuit or microprocessor (7) for controlling the electrical components, and a power supply (10) being provided between the inner and outer layers of the card (1), and wherein the inner side of the two-layered part (2) comprises cut-outs (4) through which various light effects of the light elements (5) can shine through and whe

Abstract: The present invention relates to materials and methods for components of lithium batteries, such as metal anodes having a protective coating.

Abstract: The present invention relates to methods of preparing a thin layer comprising lithium. One or more interlayer materials are applied onto a substrate to form an interlayer material coated substrate. The interlayer material coated substrate is heated to an elevated temperature. One or more metal layers are applied onto the interlayer material coated substrate, wherein the metal layer comprises lithium.

Abstract: A device includes a first vertical stack of first nanostructures formed over a substrate, a second vertical stack of second nanostructures adjacent to the first vertical stack, and a first gate structure adjacent the first nanostructures. The first gate structure includes a first gate portion between the first nanostructures, and a second gate portion extending from a first sidewall of the first gate portion to a second sidewall of the first gate portion. The second sidewall is between the first sidewall and the substrate, and is a different material than the first gate portion. A second gate structure is adjacent the second nanostructures, and a second wall structure is between the second gate portion and the second gate structure.

Abstract: A pixel sensor may include a main deep trench isolation (DTI) structure and one or more sub-DTI structures in a substrate of the pixel sensor to increase the quantum efficiency of the pixel sensor at large incident angles. The one or more sub-DTI structures may be located within the perimeter of the main DTI structure and above a photodiode. The one or more sub-DTI structures may be configured to provide a path of travel for incident light into the photodiode from large incident angles in that the one or more sub-DTI structures may be filled with an oxide material to increase light penetration into the one or more sub-DTI structures. This may reduce reflections at a top surface of the substrate, thereby permitting incident light to refract into the substrate and toward the photodiode.