Abstract: A semiconductor structure includes a first stack of active channel layers and a second stack of active channel layers disposed over a semiconductor substrate, where the second stacking include a dummy channel layer and the first stack is free of any dummy channel layer, a gate structure engaged with the first stack and the second stack, and first S/D features disposed adjacent to the first stack and second S/D features disposed adjacent to the second stack, where the second S/D features overlap with the dummy channel layer.

Abstract: A device includes a substrate, a first semiconductor channel over the substrate, a second semiconductor channel over the substrate and laterally offset from the first semiconductor channel, and a third semiconductor channel over the substrate and laterally offset from the second semiconductor channel. A first gate structure, a second gate structure, and a third gate structure are over and lateral surround the first, second, and third semiconductor channels, respectively. A first inactive fin is between the first gate structure and the second gate structure, and a second inactive fin is between the second gate structure and the third gate structure. A bridge conductor layer is over the first, second, and third gate structures, and the first and second inactive fins. A dielectric plug extends from an upper surface of the second inactive fin, through the bridge conductor layer, to at least an upper surface of the bridge conductor layer.

Abstract: Method, apparatus and systems are described to allow a base station to configure a logical channel or resources for sidelink communications. In one example aspect, a method for wireless communication includes receiving, by a user equipment, a message from a communication node. The message includes information for configuring a logical channel for a sidelink transmission. The method also includes configuring, a Medium Access Control (MAC) entity with the logical channel according to the information.

Abstract: The present disclosure provides a backlight module and a display device. The backlight module includes a light source structure and an optical film. The light source structure includes a substrate, plural light-emitting units and a package structure. The light-emitting units are disposed on the substrate. The package structure covers the light-emitting units, and the package structure has plural convex portions. The optical film is disposed on the light source structure, and the optical film is in contact with the convex portions of the package structure.

Abstract: A cord retractor for a window covering comprises a housing and a driving wheel, a reeling wheel, a spring, a friction member and a unidirectional transmission mechanism. The driving wheel and the reeling wheel can rotate with each other. The spring is coupled with the driving wheel and is wound on or unwound from the driving wheel according to a rotating direction of the driving wheel. The friction member is in a closed loop shape and surrounding a shaft of the housing. The unidirectional transmission mechanism is coupled with the friction member and the reeling wheel, and operated in different operation modes according to a rotating direction of the reeling wheel, by which the friction member provides constant resistance to the rotation of the reeling wheel when the reeling wheel rotates in a first direction, and stops providing resistance when the reeling wheel rotates in a second direction.

Abstract: A nuclear battery module is adapted for a nuclear battery. The nuclear battery module includes a radioactive unit and at least one energy conversion unit. The radioactive unit includes a soft substrate and at least one radioactive layer disposed on the soft substrate. The at least one radioactive layer includes a ?-ray source. The at least one energy conversion unit includes a flexible carrier layer, an N-type semiconductor layer disposed on the flexible carrier layer, and a P-type semiconductor layer disposed on the N-type semiconductor layer opposite to the flexible carrier layer. The at least one energy conversion unit is disposed on the radioactive unit in a manner such that the flexible carrier layer is proximate to the radioactive unit.

Abstract: A semiconductor device structure and a formation method are provided. The method includes forming a channel structure over a substrate and forming a protective spacer over sidewalls of the channel structure. The method also includes forming an insulating wall adjacent to an end of the channel structure. The method further includes removing the protective spacer to expose the channel structure. In addition, the method includes forming a metal gate stack surrounding an intermediate portion of the channel structure.

Abstract: A method for simulating conveyors includes receiving conveyor content for each cycle, the conveyor content including over-cycle distributions each specific to a vehicle group at a footprint of each conveyor for a footprint cycle time, determining a cumulative probability, for each footprint cycle time, across all of the footprints of the conveyor, of one or more of the footprints of the conveyor having that cycle time or less, and determining an individual probability, for each footprint cycle time, across all of the footprints of the conveyor, of the conveyor having that cycle time. The method further includes receiving a vehicle dispatch strategy and generating an alert indicating an over-cycle risk for the strategy based on the individual probabilities, and/or performing a discrete event simulation of the conveyors using one of the individual probabilities for each cycle and for each conveyor. Other examples systems and methods are also disclosed.

Abstract: This document generally relates to a systems, apparatus, devices, and methods for wireless communication. In an implementation, a first user device: performs a listen-before-talk (LBT) procedure in an unlicensed carrier for a sidelink transmission; determines a result of the LBT procedure; in response to determining that the result is a LBT success, transmits a sidelink signal on a channel in the unlicensed carrier to a second user device; and in response to determining that the result is a LBT failure, a physical layer entity of the first user device sends a LBT failure indication to a medium access control (MAC) layer entity of the first user device.

Abstract: Gate cutting techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is less than the first dielectric constant. A gate isolation end cap may be disposed on the gate isolation fin to provide additional isolation.

Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a first base portion and a second base portion, an isolation feature sandwiched between the first base portion and the second base portion, a center dielectric fin over the isolation feature, a first anti-punch-through (APT) feature over the first base portion, a second APT feature over the second base portion, a first stack of channel members over the first APT feature, and a second stack of channel members over the second APT feature. The center dielectric fin is sandwiched between the first stack of channel members and the second stack of channel members as well as between the first APT feature and the second APT feature.

Abstract: The present disclosure provides to a processing device and a processing method for a ray tracing acceleration structure. The processing device includes a machine-readable storage medium and a processor. The processor executes a descriptor to simulate the interaction between the ray with the scene, and the descriptor includes a first pointer and a second pointer. The processor obtains the TLAS by using the first pointer. The processor traverses the TLAS to find a leaf node in the TLAS that intersects the ray, and the intersected leaf node includes an instance identifier. The processor obtains the intersected instance record from the instance buffer pointed to by the second pointer by using the instance identifier, and the intersected instance record includes a third pointer. The processor obtains the BLAS by using the third pointer. The processor traverses the BLAS to find a primitive node in the BLAS that intersects the ray.

Abstract: An information processing method, an interconnection device, and a computer-readable storage medium are provided. The interconnection device includes a request processing module configured for: receiving a data access request from at least one processor, wherein the data access request comprises a merge bit, a multicast group identifier (MGID), and a multicast transaction identifier (MTID); determining whether the data access request is a multicast request; determining whether the interconnection device receives other multicast requests if it is determined that the data access request is a multicast request based on the MGID, the MTID, and a static routing policy of a multicast group; and obtaining the other multicast requests if it is determined that the interconnection device receives the other multicast requests, merging the multicast request with the other multicast requests into a merged request, and forwarding the merged request to a next-hop device of the interconnection device.

Abstract: Methods, systems, and devices for link measurements of vehicular device-to-device links in mobile communication technology are described. An exemplary method for wireless communication includes receiving, by a first wireless device, a device-to-device link measurement configuration, and performing a device-to-device link measurement procedure. Another exemplary method for wireless communication includes receiving, by a first wireless device, a device-to-device link monitoring configuration, and performing a device-to-device link monitoring procedure. Yet another exemplary method for wireless communication includes receiving, by a first wireless device, a device-to-device link maintenance configuration, and performing a device-to-device link maintenance procedure.

Abstract: A memory cell includes a device layer including a plurality of transistors and an interconnect structure disposed over the device layer. Each of the transistors includes a gate structure extending lengthwise in a first direction. The interconnect structure includes a bottommost metal line layer electrically coupled to the transistors in the device layer. The bottommost metal line layer includes metal lines arranged in first, second, third, fourth, fifth, and sixth metal tracks in order from first to sixth along the first direction. A distance between any adjacent two of the first, second, third, fourth, fifth, and six metal tracks measured along the first direction is uniform. The first metal track includes a metal line electrically coupled to an electric ground of the memory cell. The sixth metal track includes a metal line electrically coupled to a power supply of the memory cell.

Abstract: Some implementations described herein provide an optoelectronic device and methods of formation. The optoelectronic device is fabricated using a series of operations that includes a patterning operation using a layer of a negative photoresist material, followed by a single dry etch operation, a single wet strip operation, and a single wet etch operation. The series of operations may include a reduced number of operations relative to another series of operations that include a patterning operation using a layer of a positive photoresist material. Through the reduced number of operations, handling-induced damage to the device may be reduced. Additionally, the high absorption structure may include a quantum efficiency that is greater relative to another quantum efficiency of another high absorption structure formed through the series of operations that include the patterning operation using the layer of the positive photoresist material.

Abstract: A semiconductor structure includes a memory cell, a logic cell, and a transition region between the memory cell and the logic cell. The memory cell includes a first active region and a plurality of first gate structures with a gate pitch. The logic cell includes a second active region and a plurality of second gate structures with the gate pitch. The transition region includes a first dielectric feature and a second dielectric feature. The first dielectric feature divides the first active region into a first segment partially in the transition region and a second segment fully in the transition region. The second dielectric feature divides the second active region into a third segment partially in the transition region and a fourth segment fully in the transition region.

Abstract: A memory cell includes a first active region providing a plurality of first nano-structures for a write-port pass-gate transistor, a second active region providing a plurality of second nano-structures for a write-port pull-up transistor, and a third active region providing a plurality of third nano-structures for a read-port pull-down transistor. The first active region has a first width, the second active region has a second width, and the third active region having a third width. The third width is larger than the first width, and the first width is larger than the second width.

Abstract: A memory cell includes first and second active regions extending lengthwise in a first direction, and first, second, third, and fourth gate structures arranged in order from first to fourth along the first direction. Each of the first, second, third, and fourth gate structures extends lengthwise in a second direction that is perpendicular to the first direction. The first, second, third, and fourth gate structures are configured to engage the first and second active regions in forming first, second, third, fourth, fifth, and sixth transistors of a write-port of the memory cell. The memory cell also includes a fifth gate structure configured to engage the second active region in forming a seventh transistor of a read-port of the memory cell.

Abstract: A semiconductor structure includes a memory cell, one or more logic cells configured to provide logic function to the memory cell, and an interconnect structure disposed over the memory cell and the one or more logic cells. The interconnect structure includes a bit line, a bit line bar, a first voltage line, and a second voltage line located in a same metal line layer of the interconnect structure. At least one of the bit line and the bit line bar extends from inside a boundary of the one or more logic cells and into a boundary of the memory cell. At least one of the first and second voltage lines extends from inside the boundary of the one or more logic cells and into the boundary of the memory cell.