Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain epitaxial feature, a second source/drain epitaxial feature disposed adjacent the first source/drain epitaxial feature, a first dielectric layer disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a first dielectric spacer disposed under the first dielectric layer, and a second dielectric layer disposed under the first dielectric layer and in contact with the first dielectric spacer. The second dielectric layer and the first dielectric spacer include different materials.

Abstract: This disclosure provides for robust isolation across the SOI structure. In contrast to forming a charge trap layer in specific areas on the structure, a charge trap layer may be built across the insulating/substrate interface. The charge trap layer may be an implantation layer formed throughout and below the insulation layer. Devices built on this SOI structure have reduced cross-talk between the devices. Due to the uniform structure, isolation is robust across the structure and not confined to certain areas. Additionally, deep trench implantation is not required to form the structure, eliminating cost. The semiconductor-on-insulator substrate may include an active silicon layer over an oxide layer. The oxide layer may be over a charge trap layer. The charge trap layer may be over a silicon substrate.

Abstract: This disclosure relates to methods and apparatus for packet rerouting. In one embodiment, a method of packet rerouting includes receiving, by a wireless node from a donor central unit (CU), packet rerouting configuration information, and rerouting, by the wireless node, a transmission of a packet from a first transmission path to a second transmission path in response to, at least in part, the packet rerouting configuration information.

Abstract: A semiconductor structure includes a stack of semiconductor layers disposed over a substrate, a metal gate structure disposed over and interleaved with the stack of semiconductor layers, the metal gate structure including a gate electrode disposed over a gate dielectric layer, a first isolation structure disposed adjacent to a first sidewall of the stack of semiconductor layers, where the gate dielectric layer fills space between the first isolation structure and the first sidewall of the stack of semiconductor layers, and a second isolation structure disposed adjacent to a second sidewall of the stack of semiconductor layers, where the gate electrode fills the space between the second isolation structure and the second sidewall of the stack of semiconductor layers.

Abstract: An integrated circuit includes a first nanosheet transistor and a second nanosheet transistor on a substrate. The first and second nanosheet each include gate electrodes. A gate isolation structure extends from a backside of the substrate between the gate electrodes. The gate isolation structure physically and electrically isolates the first and second gate electrodes from each other.

Abstract: Methods and devices that include a multigate device having a channel layer disposed between a source feature and a drain feature, a metal gate that surrounds the channel layer, and a first air gap spacer interposing the metal gate and the source feature and a second air gap spacer interposing the metal gate and the drain feature. A backside contact extends to the source feature. A power line metallization layer is connected to the backside contact.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. A photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. The passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer.

Abstract: This disclosure relates to methods and devices for wireless sidelink resource allocation for a user equipment (UE) assisted by an anchor UE. Various mechanisms are disclosed for handling releasing of the anchor UE initiated by either the anchor UE or the assisted UE, and for handling sidelink resources already allocated to the UE by the anchor UE prior to the release. Additional mechanisms are disclosed for using an anchor UE to assist in allocating sidelink resources to multiple UEs configurable in a shared manner or non-shared manner.

Abstract: A pixel sensor may include a layer stack to reduce and/or block the effects of plasma and etching on a photodiode and/or other lower-level layers. The layer stack may include a first oxide layer, a layer having a band gap that is approximately less than 8.8 electron-Volts (eV), and a second oxide layer. The layer stack may reduce and/or prevent the penetration and absorption of ultraviolet photons resulting from the plasma and etching processes, which may otherwise cause the formation of electron-hole pairs in the substrate in which the photodiode is included.

Abstract: A neutron capture therapy system is provided, including a neutron generating device and a beam shaping assembly. The neutron capture therapy system further includes a concrete wall forming a space for accommodating the neutron generating device and the beam shaping assembly and shielding radiations generated by the neutron generating device and the beam shaping assembly. A support module is disposed in the concrete wall, the support module is capable of supporting the beam shaping assembly and is used to adjust the position of the beam shaping assembly, and the support module includes concrete and a reinforcing portion at least partially disposed in the concrete. The neutron capture therapy system designs a locally adjustable support for the beam shaping assembly, so that the beam shaping assembly can meet the precision requirement, improve the beam quality, and meet an assembly tolerance of the target.

Abstract: A hybrid protective coating includes an inorganic component and an organic component such that the inorganic component includes at least one of a metal oxide, a metal fluoride, or combination thereof, and the organic component includes at least one metalcone.

Abstract: A clutch can include an input; an output; a centrifugal clutch mechanism that transfers energy from the input to the output, the centrifugal clutch mechanism including: a disk; centrifugal weights movably coupled to the disk; and a central shaft rotatable relative to the disk and extending through the disk, the central shaft comprising drive surfaces, wherein the disk is rotatably coupled to the input, wherein the output is rotatably coupled to the central shaft, wherein the centrifugal weights rotate between a disengaged position in which the centrifugal weights do not interface with drive surfaces and an engaged position in which the centrifugal weights interface with the drive surfaces, and wherein the centrifugal weights are disposed inside the perimeter of the disk when the centrifugal weights are in the engaged position.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.

Abstract: Disclosed herein are related to a memory cell including magnetic tunneling junction (MTJ) devices. In one aspect, the memory cell includes a first layer including a first transistor and a second transistor. In one aspect, the first transistor and the second transistor are connected to each other in a cross-coupled configuration. A first drain structure of the first transistor may be electrically coupled to a first gate structure of the second transistor, and a second drain structure of the second transistor may be electrically coupled to a second gate structure of the first transistor. In one aspect, the memory cell includes a second layer including a first MTJ device electrically coupled to the first drain structure of the first transistor and a second MTJ device electrically coupled to the second drain structure of the second transistor. In one aspect, the second layer is above the first layer.

Abstract: Methods and systems are provided for a natural language processing system comprising a chatbot adapted for dialog generation. In one example, the system may include a combination of a variational autoencoder (VAE) and a generative adversarial network (GAN) for generating natural responses to input queries. The VAE may convert queries into vector embeddings that may then be used by the GAN to continuously update and improve responses provided by the chatbot.

Abstract: A first gate-all-around (GAA) transistor and a second GAA transistor may be formed on a substrate. The first GAA transistor includes at least one silicon plate, a first gate structure, a first source region, and a first drain region. The second GAA transistor includes at least one silicon-germanium plate, a second gate structure, a second source region, and a second drain region. The first GAA transistor may be an n-type field effect transistor, and the second GAA transistor may be a p-type field effect transistor. The gate electrodes of the first gate structure and the second gate structure may include a same conductive material. Each silicon plate and each silicon-germanium plate may be single crystalline and may have a same crystallographic orientation for each Miller index.

Abstract: A device includes a stack of first semiconductor nanostructures over a substrate and a stack of second semiconductor nanostructures over the substrate. The device includes an isolation structure between the first and second semiconductor nanostructures. The isolation structure includes a core dielectric layer extending from below a top surface of the substrate to a level higher than all of the first and second semiconductor nanostructures. The isolation structure includes a shell dielectric layer surrounding a lower portion of the core dielectric layer and having a top surface lower than all of the semiconductor nanostructures. The spaces between the core dielectric layer and each of the semiconductor nanostructures can be filled with gate dielectric material or with remnants of the shell dielectric layer.

Abstract: Semiconductor devices and method of forming the same are provided. In one embodiment, a semiconductor device includes a first transistor and a second transistor. The first transistor includes two first source/drain features and a first number of nanostructures that are stacked vertically one over another and extend lengthwise between the two first source/drain features. The second transistor includes two second source/drain features and a second number of nanostructures that are stacked vertically one over another and extend lengthwise between the two second source/drain features.

Abstract: This disclosure relates generally to a method, device, and system for sidlink communication in wireless communications. One method performed by a CU including transmitting a first transferring message to a Central Unit (CU) of the wireless communication node, wherein the first transferring message is based on a first message associated with a relay UE in the wireless network, and wherein the first transferring message further comprises at least one of the following fields: a CU level remote UE identifier (ID) identifying a remote UE in the CU; a DU level remote UE ID identifying the remote UE in the DU; an ID of the remote UE; or a Cell Radio Network Temporary Identifier (C-RNTI) of the remote UE.

Abstract: A semiconductor structure includes a stack of semiconductor layers disposed over a substrate, a metal gate structure disposed over and interleaved with the stack of semiconductor layers, the metal gate structure including a gate electrode disposed over a gate dielectric layer, a first isolation structure disposed adjacent to a first sidewall of the stack of semiconductor layers, where the gate dielectric layer fills space between the first isolation structure and the first sidewall of the stack of semiconductor layers, and a second isolation structure disposed adjacent to a second sidewall of the stack of semiconductor layers, where the gate electrode fills the space between the second isolation structure and the second sidewall of the stack of semiconductor layers.