Abstract: A display device may include a plurality of pixels, a plurality of source lines that may provide a plurality of data line signals to the plurality of pixels, a plurality of gate lines that may provide a plurality of gate signals to a plurality of switches associated with the plurality of pixels, and a plurality of voltage gate lines disposed parallel to the plurality of source lines and coupled to the plurality of gate lines at a plurality of cross point nodes. The plurality of cross point nodes are positioned in a pseudo random order across the display device.

Abstract: The disclosure provides a stator module and a magnetic field generating structure which includes a magnetizer and an electrically conducting pipe. The electrically conducting pipe is wound around the magnetizer and has a passage inside. The passage has an outlet and an inlet opposite to each other. The electrically conducting pipe has a current input portion and a current output portion.

Abstract: A method for distributing workload among a plurality of servers each having a given workload capacity for providing a web service is provided. The method is to be implemented by a master module and includes the steps of: a) for each of the servers, determining a maximum allowable workload that is smaller than the given workload capacity; b) for each of activated one(s) of the servers operating to provide the web service, detecting a current network workload thereof; c) calculating an overall workload equal to a summation of the current network workload(s) detected in step b); and d) deactivating/activating at least one of the servers so as to adjust a number of the activated one(s) of the servers according to the overall workload calculated in step c), the current network workload(s) detected in step b), and the maximum allowable workload(s) of the activated one(s) of the servers.

Abstract: The present disclosure illustrates a motor speed curve control circuit. The motor speed curve control circuit is configured for adjusting a speed of a motor according to a motor speed curve. The motor speed curve control circuit comprises a divider resistor module, an analog-to-digital converter and an arithmetic unit. The resistor module is configured for generating at least one turning-point voltage. The turning-point voltage is used to adjust a slope of the motor speed curve. The analog-to-digital converter converts the turning-point voltage to digital form. The arithmetic unit sets a speed associated with the turning-point voltage corresponding to a first preset duty cycle in the motor speed curve, such that the motor speed curve becomes linear. The arithmetic unit generates a second pulse width modulation signal according to the adjusted motor speed curve and a first pulse width modulation signal to drive the motor.

Abstract: The disclosure provides a stator module and a magnetic field generating structure which includes a magnetizer and an electrically conducting pipe. The electrically conducting pipe is wound around the magnetizer and has a passage inside. The passage has an outlet and an inlet opposite to each other. The electrically conducting pipe has a current input portion and a current output portion.

Abstract: A display has an array of pixels controlled by display driver circuitry. Gate driver circuitry supplies gate line signals to rows of the pixels. The pixels may be liquid crystal display pixels. Each pixel may have a common electrode voltage terminal. The display may have a transparent conductive film that forms a common electrode voltage layer that overlaps that array and that is shorted to the common electrode voltage terminals of the pixels. Metal common electrode voltage lines may run across the transparent conductive film to reduce resistance. Metal common electrode voltage paths that are coupled to the metal common electrode voltage lines may run along the left and right edge of the display. Common electrode voltage compensation circuits may receive feedback from the metal common electrode voltage paths. There may be two or more common electrode voltage compensation circuits for both the left and right edges of the display.

Abstract: A display may have a first stage such as a color liquid crystal display stage and a second stage such as a monochromatic liquid crystal display stage that are coupled in tandem so that light from a backlight passes through both stages. The pixel pitch of the second stage may be greater than the pixel pitch of the first stage to ease alignment tolerances and reduce image processing complexity. The first stage may be provided with straight black masking strips, whereas the second stage may be provided with angled zigzagging black masking strips. The angle of the zigzagging black masking strips and the ratio of the pixel pitch of the second stage to that of the first stage may be selected to maximize optical transmittance while minimizing Moire effects.

Abstract: A display may have an array of pixels arranged in rows and columns. Each pixel may have a transistor for controlling the amount of output light associated with that pixel. The transistors may be thin-film transistors having active areas, first and second source-drain terminals, and gates. Gate lines may be used to distribute gate control signals to the gates of the transistors in each row. Data lines that run perpendicular to the gate lines may be used to distribute image data along columns of pixels. The gate lines may be connected to gate line extensions that run parallel to the data lines. The data lines may each overlap a respective one of the gate line extensions. Vias may be used to connect the gate line extensions to the gate lines. The gate line extensions may all have the same length.

Abstract: A display may have an array of pixels arranged in rows and columns. Each pixel may have a transistor for controlling the amount of output light associated with that pixel. The transistors may be thin-film transistors having active areas, first and second source-drain terminals, and gates. Gate lines may be used to distribute gate control signals to the gates of the transistors in each row. Data lines that run perpendicular to the gate lines may be used to distribute image data along columns of pixels. The gate lines may be connected to gate line extensions that run parallel to the data lines. The data lines may each overlap a respective one of the gate line extensions. Vias may be used to connect the gate line extensions to the gate lines. The gate line extensions may all have the same length.

Abstract: A display may have an array of pixels arranged in rows and columns. Each pixel may have a transistor for controlling the amount of output light associated with that pixel. The transistors may be thin-film transistors having active areas, first and second source-drain terminals, and gates. Gate lines may be used to distribute gate control signals to the gates of the transistors in each row. Data lines that run perpendicular to the gate lines may be used to distribute image data along columns of pixels. The gate lines may be connected to gate line extensions that run parallel to the data lines. The data lines may each overlap a respective one of the gate line extensions. Vias may be used to connect the gate line extensions to the gate lines. The gate line extensions may all have the same length.

Abstract: This invention relates to a triple immunostaining assay (ERG/TFF3/HMWCK) for sensitive and specific detection of prostate cancer. Positive staining for at least one of ERG or TFF3 combined with negative staining of HMWCK in a sample such as prostate tissue sample is indicative of cancer.

Abstract: A fabrication method of a pixel structure and a pixel structure are provided. A first patterned metal layer including scan lines and a gate is formed on a substrate. A first insulation layer, a semiconductor layer, an etching stop pattern and a metal layer are formed sequentially on the first patterned metal layer. The metal layer and the semiconductor layer are patterned to form a second patterned metal layer and a patterned semiconductor layer. The second patterned metal layer includes data lines, a source and a drain. The patterned semiconductor layer includes a first semiconductor pattern completely overlapping the second patterned metal layer and a second semiconductor pattern without overlapping the second patterned metal layer, wherein the second semiconductor pattern includes a channel pattern and a marginal pattern. The channel pattern is between the source and the drain and the marginal pattern surrounds the first semiconductor pattern.

Abstract: A method is provided for fabricating a thin-film transistor (TFT). The method includes forming a semiconductor layer over a gate insulator that covers a gate electrode, and depositing an insulator layer over the semiconductor layer, as well as etching the insulator layer to form a patterned etch-stop without losing the gate insulator. The method also includes forming a source electrode and a drain electrode over the semiconductor layer and the patterned etch-stop. The method further includes removing a portion of the semiconductor layer beyond the source electrode and the drain electrode such that a remaining portion of the semiconductor layer covers the gate insulator in a first overlapping area of the source electrode and the gate electrode and a second overlapping area of the drain electrode and gate electrode.

Abstract: A wire fusing apparatus including a first body having a first surface, a second body having a second surface, and a heating unit is provided. The second body is pivoted to the first body to rotate relatively to the first body enabling the first and second bodies to be in an expanded or a closed state. When the first and second bodies are in the closed state, the first and second surfaces define a closed containing groove for containing two independent wires butt jointed with each other. The first surface, the second surface and the containing groove each has a heat-conducting region, and the heat-conducting regions contact each other when the first and second bodies are in the closed state. The heating unit disposed on the first or second body contacts one of the heat-conducting regions for heat-fusing a butt-jointing point of the wires to form a fused wire.

Abstract: A method is provided for fabricating a thin-film transistor (TFT). The method includes forming a semiconductor layer over a gate insulator that covers a gate electrode, and depositing an insulator layer over the semiconductor layer, as well as etching the insulator layer to form a patterned etch-stop without losing the gate insulator. The method also includes forming a source electrode and a drain electrode over the semiconductor layer and the patterned etch-stop. The method further includes removing a portion of the semiconductor layer beyond the source electrode and the drain electrode such that a remaining portion of the semiconductor layer covers the gate insulator in a first overlapping area of the source electrode and the gate electrode and a second overlapping area of the drain electrode and gate electrode.

Abstract: A fabrication method of a pixel structure and a pixel structure are provided. A first patterned metal layer including scan lines and a gate is formed on a substrate. A first insulation layer, a semiconductor layer, an etching stop pattern and a metal layer are formed sequentially on the first patterned metal layer. The metal layer and the semiconductor layer are patterned to form a second patterned metal layer and a patterned semiconductor layer. The second patterned metal layer includes data lines, a source and a drain. The patterned semiconductor layer includes a first semiconductor pattern completely overlapping the second patterned metal layer and a second semiconductor pattern without overlapping the second patterned metal layer, wherein the second semiconductor pattern includes a channel pattern and a marginal pattern. The channel pattern is between the source and the drain and the marginal pattern surrounds the first semiconductor pattern.

Abstract: A method is provided for fabricating a thin-film transistor (TFT). The method includes forming a semiconductor layer over a gate insulator that covers a gate electrode, and depositing an insulator layer over the semiconductor layer, as well as etching the insulator layer to form a patterned etch-stop without losing the gate insulator. The method also includes forming a source electrode and a drain electrode over the semiconductor layer and the patterned etch-stop. The method further includes removing a portion of the semiconductor layer beyond the source electrode and the drain electrode such that a remaining portion of the semiconductor layer covers the gate insulator in a first overlapping area of the source electrode and the gate electrode and a second overlapping area of the drain electrode and gate electrode.

Abstract: A fabrication method of a pixel structure and a pixel structure are provided. A first patterned metal layer including scan lines and a gate is formed on a substrate. A first insulation layer, a semiconductor layer, an etching stop pattern and a metal layer are formed sequentially on the first patterned metal layer. The metal layer and the semiconductor layer are patterned to form a second patterned metal layer and a patterned semiconductor layer. The second patterned metal layer includes data lines, a source and a drain. The patterned semiconductor layer includes a first semiconductor pattern completely overlapping the second patterned metal layer and a second semiconductor pattern without overlapping the second patterned metal layer, wherein the second semiconductor pattern includes a channel pattern and a marginal pattern. The channel pattern is between the source and the drain and the marginal pattern surrounds the first semiconductor pattern.

Abstract: An embodiment disclosed a system for collaborative positioning calibration, comprising at least one reference station and at least one client. The reference station uses a known position and a satellite signal transmitted by at least one satellite to compute a pseudo-range difference of the reference station position and the satellite position, and then broadcasts an area calibration data including at least one pseudo-range difference to at least one client. Based on the area calibration data, the client computes at least one pseudo-range calibration data and outputs a calibrated position of global positioning system.