Patents by Inventor Lin Chu

Lin Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240095141
    Abstract: A method and an apparatus for displaying an information flow on a terminal device, an electronic device, a computer-readable storage medium, and a computer program product are provided. An implementation is: in response to detecting an activation operation on an application for displaying the information flow, reproducing, on the terminal device, a first page displayed on the terminal device when the application is last switched to running in the background or closed; and in response to determining that a time interval between the activation operation and the application being last switched to running in the background or closed does not exceed a first threshold, displaying a second page as a continuation of a content entry displayed in the first page, where the second page includes at least one first content entry cached in the terminal device before the activation operation but not displayed in the first page.
    Type: Application
    Filed: March 21, 2022
    Publication date: March 21, 2024
    Inventors: Yifan ZHANG, Yuqi WANG, Linfei CHU, Jing NING, Kunjie SUN, Yuhang ZHENG, Naifei SONG, Shujuan ZHANG, Lin LIU, Xunzhuo JU, Zhengwei CHEN, Wei ZHANG, Hua ZHANG, Congjun ZHOU, Tingkang WU, Tengfei LV, Hanmeng LIU, Lei WANG
  • Publication number: 20240096880
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first channel structure configured to transport charge carriers within a first transistor device and a first gate electrode layer wrapping around the first channel structure. A second channel structure is configured to transport charge carriers within a second transistor device. A second gate electrode layer wraps around the second channel structure. The second gate electrode layer continuously extends from around the second channel structure to cover the first gate electrode layer. A third channel structure is configured to transport charge carriers within a third transistor device. A third gate electrode layer wraps around the third channel structure. The third gate electrode layer continuously extends from around the third channel structure to cover the second gate electrode layer.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 21, 2024
    Inventors: Mao-Lin Huang, Chih-Hao Wang, Kuo-Cheng Chiang, Jia-Ni Yu, Lung-Kun Chu, Chung-Wei Hsu
  • Patent number: 11935349
    Abstract: Techniques for managing access to a physical area are provided. In one technique, first data is extracted from a digital file. Based on identification data within the first data, a database is searched. A data item in the database is identified that matches the identification data. The first data is associated with the data item. After associating the first data with the data item, code data is generated. Encoded data that encodes the code data is then generated. The encoded data is sent over a computer network to a mobile device, or an account, of a user that is associated with the data item.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: March 19, 2024
    Assignee: Ricoh Company, Ltd.
    Inventors: Candice Lin, Te-Yu Chu, Phuc Nguyen, Yuwen Wu, Kaoru Watanabe, Shun Tanaka, Jayasimha Nuggehalli
  • Publication number: 20240085803
    Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-I Yang, Wei-Chen Chu, Hsiang-Wei Liu, Shau-Lin Shue, Li-Lin Su, Yung-Hsu Wu
  • Patent number: 11929363
    Abstract: In some embodiments, a semiconductor device is provided, including a first doped region of a first conductivity type configured as a first terminal of a first diode, a second doped region of a second conductivity type configured as a second terminal of the first diode, wherein the first and second doped regions are coupled to a first voltage terminal; a first well of the first conductivity type surrounding the first and second doped regions in a layout view; a third doped region of the first conductivity type configured as a first terminal, coupled to an input/output pad, of a second diode; and a second well of the second conductivity type surrounding the third doped region in the layout view. The second and third doped regions, the first well, and the second well are configured as a first electrostatic discharge path between the I/O pad and the first voltage terminal.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin Peng, Li-Wei Chu, Ming-Fu Tsai, Jam-Wem Lee, Yu-Ti Su
  • Publication number: 20240074448
    Abstract: The present invention relates to a method for moderately increasing the content of dimethyl disulfide in casein-containing processed cheese. The method includes the following steps: taking a cheese powder, adding chymosin for enzymolysis, and subjecting a material obtained after the enzymolysis to puffing and drying to obtain a modified cheese powder; preparing materials; taking the modified cheese powder, heating the modified cheese powder under stirring until the cheese powder is melt, adding sodium bicarbonate to adjust the pH to 6-7, and adding papain for enzymolysis; taking a material obtained after the enzymolysis, adding butter, a skimmed milk powder, fructo-oligosaccharide and water for mixing by stirring, and then adding an emulsifying salt, glutamine transaminase and salt for uniform heating and stirring to obtain a mixture; and subjecting the mixture to heat treatment, hot filling and cooling in sequence to obtain processed cheese.
    Type: Application
    Filed: September 6, 2022
    Publication date: March 7, 2024
    Applicant: ZHEJIANG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Gongnian Xiao, Kewei Cheng, Ruosi Fang, Lin Li, Bingquan Chu, Xin Lu, Jinyan Gong, Xian Li
  • Patent number: 11915954
    Abstract: A die sorter tool may include a first conveyor, and a first lane to receive, from one or more load ports and via the first conveyor, a carrier with a set of dies. The die sorter tool may include a die flip module to receive the carrier from the first lane, manipulate one or more dies of the set of dies by changing orientations of the one or more dies, and return the one or more dies to the carrier after manipulating the one or more dies and without changing positions of the one or more dies within the carrier. The die sorter tool may include a second conveyor, and a second lane to receive, via the second conveyor, the carrier from the die flip module, and provide, via the first conveyor, the carrier to the one or more load ports.
    Type: Grant
    Filed: January 30, 2023
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hung Huang, Cheng-Lung Wu, Zheng-Lin He, Yang-Ann Chu, Jiun-Rong Pai, Hsuan Lee
  • Patent number: 11915937
    Abstract: A method includes forming a plurality of nanostructures over a substrate; etching the plurality of nanostructures to form recesses; forming source/drain regions in the recesses; removing first nanostructures of the plurality of nanostructures leaving second nanostructures of the plurality of nanostructures; depositing a gate dielectric over and around the second nanostructures; depositing a protective material over the gate dielectric; performing a fluorine treatment on the protective material; removing the protective material; depositing a first conductive material over the gate dielectric; and depositing a second conductive material over the first conductive material.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yi Lee, Mao-Lin Huang, Lung-Kun Chu, Huang-Lin Chao, Chi On Chui
  • Publication number: 20240052040
    Abstract: Pharmaceutical preparations containing polypeptides having particular sialylation patterns, and methods for the treatment of immune-related thrombocytopenia with such preparations, are described.
    Type: Application
    Filed: April 19, 2023
    Publication date: February 15, 2024
    Inventors: Birgit C. Schultes, Chia Lin Chu, Laura Rutitzky, Lynn Zhang, Leona E. Ling
  • Publication number: 20240021642
    Abstract: The present disclosure relates to an image sensor comprising a substrate. A photodetector is in the substrate. A trench is in the substrate and is defined by sidewalls and an upper surface of the substrate. A first isolation layer extends along the sidewalls and the upper surface of the substrate that define the trench. The first isolation layer comprises a first dielectric material. A second isolation layer is over the first isolation layer. The second isolation layer lines the first isolation layer. The second isolation layer comprises a second dielectric material. A third isolation layer is over the second isolation layer. The third isolation layer fills the trench and lines the second isolation layer. The third isolation layer comprises a third material. A ratio of a first thickness of the first isolation layer to a second thickness of the second isolation layer is about 0.17 to 0.38.
    Type: Application
    Filed: July 20, 2023
    Publication date: January 18, 2024
    Inventors: Min-Ying Tsai, Cheng-Te Lee, Rei-Lin Chu, Ching I Li, Chung-Yi Yu
  • Patent number: 11866632
    Abstract: Liquid-crystal polymer is composed of the following repeating units: 10 mol % to 35 mol % of 10 mol % to 35 mol % of 10 mol % to 50 mol % of and 10 mol % to 40 mol % of 10 mol % to 40 mol % of or a combination thereof. Each of AR1, AR2, AR3, and AR4 is independently AR5 or AR5-Z-AR6, in which each of AR5 and AR6 is independently or a combination thereof, and Z is —O—, or C1-5 alkylene group. Each of X and Y is independently H, C1-5 alkyl group, CF3, or wherein R2 is H, CH3, CH(CH3)2, C(CH3)3, CF3, or n=1 to 4; and wherein R1 is C1-5 alkylene group.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: January 9, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Lin Chu, Jen-Chun Chiu, Zu-Chiang Gu, Po-Hsien Ho, Meng-Hsin Chen, Chih-Hsiang Lin
  • Patent number: 11862612
    Abstract: Various embodiments of the present disclosure are directed towards a three-dimensional (3D) trench capacitor, as well as methods for forming the same. In some embodiments, a first substrate overlies a second substrate so a front side of the first substrate faces a front side of the second substrate. A first trench capacitor and a second trench capacitor extend respectively into the front sides of the first and second substrates. A plurality of wires and a plurality of vias are stacked between and electrically coupled to the first and second trench capacitors. A first through substrate via (TSV) extends through the first substrate from a back side of the first substrate, and the wires and the vias electrically couple the first TSV to the first and second trench capacitors. The first and second trench capacitors and the electrical coupling therebetween collectively define the 3D trench capacitor.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xin-Hua Huang, Chung-Yi Yu, Yeong-Jyh Lin, Rei-Lin Chu
  • Publication number: 20230420493
    Abstract: A metal-insulator-metal (MIM) capacitor and methods of forming the same are described. In some embodiments, the method includes forming an opening having a first depth in one or more dielectric layers, depositing a layer in the opening and on the one or more dielectric layers, performing an anisotropic etch process to remove portions of the layer formed on horizontal surfaces, extending the opening to a second depth in the one or more dielectric layers, removing the layer, extending the opening to a third depth in the one or more dielectric layers, and forming a MIM capacitor in the opening.
    Type: Application
    Filed: June 27, 2022
    Publication date: December 28, 2023
    Inventors: Hsing-Lien LIN, Hai-Dang TRINH, Yao-Wen CHANG, Jui-Lin CHU, Cheng-Te LEE
  • Publication number: 20230387189
    Abstract: A semiconductor structure includes a capacitor structure and a contact structure. The capacitor structure includes an electrode layer, a protective dielectric layer, and a capacitor dielectric layer. The protective dielectric layer covers a top surface of the electrode layer. The capacitor dielectric layer is on the protective oxide layer. The contact structure penetrates the protective oxide layer and electrically connects to the electrode layer.
    Type: Application
    Filed: May 26, 2022
    Publication date: November 30, 2023
    Inventors: JUI-LIN CHU, SZU-YU WANG, CHING I LI
  • Publication number: 20230387856
    Abstract: A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 30, 2023
    Inventors: Chia-Chung CHEN, Chi-Feng HUANG, Victor Chiang LIANG, Fu-Huan TSAI, Hsieh-Hung HSIEH, Tzu-Jin YEH, Han-Min TSAI, Hong-Lin CHU
  • Publication number: 20230378162
    Abstract: In an integrated circuit (IC) fabrication process, devices or sub-circuits are fabricated in respective first and second electrical isolation regions. A back-to-back (B2B) diodes sub-circuit is fabricated in a third electrical isolation region, which includes a first diode whose cathode is connected with a first terminal and whose anode is connected with a second terminal, and a second diode whose anode is connected with the first terminal and whose cathode is connected with the second terminal. Electrostatic discharge protection is provided to the first and second electrical isolation regions by electrically connecting the first terminal of the B2B diodes sub-circuit with a VSS power supply terminal of the first device or sub-circuit and the second terminal of the B2B diodes sub-circuit with a VSS power supply terminal of the second device or sub-circuit. Thereafter, the first device or sub-circuit and the second device or sub-circuit are electrically connected.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company LTD
    Inventors: Hsi-Yu Kuo, Tsung-Yuan Chen, Yu-Lin Chu, Chih-Wei Hsu
  • Publication number: 20230365732
    Abstract: The present application provides a binder and a lithium-ion battery including the binder. The binder is rich in amino groups, has strong alkali resistance and is not easy to decompose. Besides, rich amino groups in the binder are prone to form hydrogen bonds, so that the binder more fully coats an active material and can enhance an acting force between the active material and a current collector, improve a peeling strength of an electrode piece, and significantly improve a cycling performance, expansion rate, and rate capability of lithium-ion batteries using the binder.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 16, 2023
    Inventors: Lin CHU, Panlong GUO, Weiping CHEN, Suli LI, Junyi LI
  • Publication number: 20230369599
    Abstract: The present application provides a boric acid derivative modified binder and a lithium-ion battery including the binder. Surfaces of emulsion particles of the binder are rich in boric acid groups (—B(OH)2). When the binder is applied to an electrode piece of the battery, the boric acid groups can be subjected to a dehydration condensation reaction with —OH in sodium carboxymethyl cellulose dispersant, or with —OH in a functional monomer during the drying process of the electrode piece, to form a three-dimensional network, increasing the bonding force and greatly improving the peeling strength of the electrode piece. The binder can also significantly improve the cycle performance of the lithium-ion battery, thereby prolonging the cycle life of the lithium-ion battery.
    Type: Application
    Filed: July 24, 2023
    Publication date: November 16, 2023
    Inventors: Lin CHU, Panlong GUO, Weiping CHEN, Suli LI, Junyi LI
  • Publication number: 20230341765
    Abstract: A method includes: providing a first design layout including a plurality of cells; updating a first cell of the plurality of cells using optical proximity correction to provide a first updated cell and a data set; and updating a second cell from remaining cells in the first design layout based on the data set and a model without involvement of optical proximity correction to provide a second updated cell, wherein the model includes hidden layers including nodes and is trained to obtaining converged values of the nodes of the hidden layers through providing a mapping of edge segments before lithography enhancement and edge segments after lithography enhancement using optical proximity correction, and wherein at least one of the providing, and updating is executed by one or more processors.
    Type: Application
    Filed: June 29, 2023
    Publication date: October 26, 2023
    Inventors: WEI-LIN CHU, HSIN-LUN TSENG, SHENG-WEN HUANG, CHIH-CHUNG HUANG, CHI-MING TSAI
  • Patent number: 11797108
    Abstract: A mouse device includes a roller module. The roller module includes a base member, a scroll wheel, a magnetic conductor, a swingable arm, a driving motor and an actuating element. The scroll wheel is installed on the base member. The magnetic conductor is located beside the scroll wheel. When the scroll wheel is rotated, the magnetic conductor is correspondingly rotated. The swingable arm is installed on the base member. The swingable arm includes a magnetic element. The swingable arm is swingable relative to the magnetic conductor. When the swingable arm is swung to a first position, the magnetic element is aligned with the magnetic conductor. Consequently, a magnetic attraction force between the magnetic element and the magnetic conductor is generated. When the swingable arm is swung to a second position, the magnetic attraction force between the magnetic element and the magnetic conductor is eliminated.
    Type: Grant
    Filed: February 2, 2023
    Date of Patent: October 24, 2023
    Assignee: PRIMAX ELECTRONICS LTD.
    Inventors: Chun-Nan Su, Chun-Che Wu, Shu-An Huang, Chun-Lin Chu, Ming-Hao Hsieh, Sheng-An Tsai, Li-Kuei Cheng