Abstract: Various embodiments of the present application are directed towards a metal-insulator-metal (MIM) capacitor. The MIM capacitor comprises a bottom electrode disposed over a semiconductor substrate. A top electrode is disposed over and overlies the bottom electrode. A capacitor insulator structure is disposed between the bottom electrode and the top electrode. The capacitor insulator structure comprises at least three dielectric structures vertically stacked upon each other. A bottom half of the capacitor insulator structure is a mirror image of a top half of the capacitor insulator structure in terms of dielectric materials of the dielectric structures.

Abstract: A metal probe structure and a method for fabricating the same are provided. The metal probe structure includes a multi-layer substrate, a first flexible dielectric layer, a second flexible dielectric layer, and a plurality of first metal components. The first flexible dielectric layer is disposed over the multi-layer substrate and has a conductive layer formed thereover. The second flexible dielectric layer is disposed over the first flexible dielectric layer to cover the conductive layer. The plurality of first metal components is disposed over the conductive layer and partially in the second flexible dielectric layer to serve as a metal probe.

Abstract: A keyboard device includes a keyboard module and a palm rest module. The palm rest module is arranged beside a lateral side of the keyboard module, and supports a wrist of a user. The palm rest module includes a pedestal, a casing and an adjusting element. The casing is disposed on the pedestal. The adjusting element is arranged between the pedestal and the casing. A position of the casing relative to the pedestal is adjustable through the adjusting element. In a first usage state, the casing is moved toward the keyboard module or moved away from the keyboard module through the adjusting element. In a second usage state, the casing is rotated about the adjusting element and relative to the keyboard module, so that an included angle is formed between the casing and the lateral side of the keyboard module.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a first well, a second well and doped regions. The substrate has heavily doped and lightly doped regions over the heavily doped region. The first wells are disposed in the lightly doped region and arranged as an array. The first wells have a conductive type opposite to a conductive type of the heavily doped and lightly doped regions. The second well is disposed in the substrate over the lightly doped region, and has an active region defined by an isolation structure. The first wells are overlapped with the second well. Top ends of the first wells are lower than a bottom end of the second well. The doped regions are separately located in the active region, and have a conductive type opposite to a conductive type of the second well.

Abstract: According to an aspect, an image sensor package includes a substrate, an image sensor die coupled to the substrate, and a transparent member including a first surface and a second surface, where the second surface of the transparent member is coupled to the image sensor die via one or more dam members such that an empty space exists between an active area of the image sensor die and the second surface of the transparent member. The image sensor package includes a light blocking member coupled to or defined by the transparent member.

Abstract: Various embodiments of the present application are directed towards a metal-insulator-metal (MIM) capacitor. The MIM capacitor comprises a bottom electrode disposed over a semiconductor substrate. A top electrode is disposed over and overlies the bottom electrode. A capacitor insulator structure is disposed between the bottom electrode and the top electrode. The capacitor insulator structure comprises at least three dielectric structures vertically stacked upon each other. A bottom half of the capacitor insulator structure is a mirror image of a top half of the capacitor insulator structure in terms of dielectric materials of the dielectric structures.

Abstract: A keyboard device includes a casing and at least one supporting leg. The supporting leg includes a first supporting part, a second supporting part and a pivotal shaft. The supporting leg is pivotally coupled to an accommodation space of the casing through the pivotal shaft. The pivotal shaft is rotatable relative to the casing. Consequently, the supporting leg can be switched between a stored state and a supporting state. When the supporting leg is in the stored state, the supporting leg is accommodated within the accommodation space, and the accommodation space is covered by the first supporting part and the second supporting part. While the supporting leg is switched from the stored state to the supporting state, the first supporting part is pushed into the accommodation space in response to an external force, and the second supporting part is correspondingly moved away from the accommodation space.

Abstract: A key structure includes a frame member, a keycap and a stabilizer bar. The keycap includes first and second clamping members. The first clamping member includes a first upper stopping part, a first lower stopping part and a first lateral stopping part. The second clamping member includes a second upper stopping part, a second lower stopping part and a second lateral stopping part. The stabilizer bar includes a shaft part, a first leg part and a second leg part. The shaft part is received within a hook of the frame member. The first leg part is received within the first clamping member. The second leg part is received within the second clamping member. The first lateral stopping part is pushed against the first leg part along a first direction. The second lateral stopping part is pushed against the second leg part along a second direction.

Abstract: In accordance with some embodiments, a method for processing semiconductor wafer is provided. The method includes introducing a first processing gas of an atomic layer deposition (ALD) process on the semiconductor substrate in a chamber; introducing a second processing gas of the ALD process on the semiconductor substrate in the chamber; creating an exhaust flow from the chamber; monitoring a concentration of the first processing gas of the ALD process in the exhaust flow; in response to the monitored concentration of the first processing gas of the ALD process in the exhaust flow, introducing a cleaning gas into the chamber.

Abstract: A heat dissipation device includes a base having a first surface in contact with at least one heat source and an opposite second surface having a heat dissipation zone upward extended therefrom; an auxiliary heat dissipation zone horizontally extended from one of four lateral sides or directions of the heat dissipation zone; an air guiding section defined at the auxiliary heat dissipation zone; and at least one upward indented zone formed between the auxiliary heat dissipation zone and the side of the heat dissipation zone having the auxiliary heat dissipation zone sideward sidewardly extended from a higher portion thereof. With these arrangements, the heat dissipation device can guide air flow currents directly or indirectly to a plurality of heat sources located corresponding to the heat dissipation zone and the auxiliary heat dissipation zone at the same time to cool them.

Abstract: The present disclosure relates to an image sensor comprising a substrate. A photodetector is in the substrate. A trench is in the substrate and is defined by sidewalls and an upper surface of the substrate. A first isolation layer extends along the sidewalls and the upper surface of the substrate that define the trench. The first isolation layer comprises a first dielectric material. A second isolation layer is over the first isolation layer. The second isolation layer lines the first isolation layer. The second isolation layer comprises a second dielectric material. A third isolation layer is over the second isolation layer. The third isolation layer fills the trench and lines the second isolation layer. The third isolation layer comprises a third material. A ratio of a first thickness of the first isolation layer to a second thickness of the second isolation layer is about 0.17 to 0.38.

Abstract: Various embodiments of the present disclosure are directed towards a three-dimensional (3D) trench capacitor, as well as methods for forming the same. In some embodiments, a first substrate overlies a second substrate so a front side of the first substrate faces a front side of the second substrate. A first trench capacitor and a second trench capacitor extend respectively into the front sides of the first and second substrates. A plurality of wires and a plurality of vias are stacked between and electrically coupled to the first and second trench capacitors. A first through substrate via (TSV) extends through the first substrate from a back side of the first substrate, and the wires and the vias electrically couple the first TSV to the first and second trench capacitors. The first and second trench capacitors and the electrical coupling therebetween collectively define the 3D trench capacitor.

Abstract: A multi-layer substrate structure which can be peeled off precisely includes: a substrate; a first flexible dielectric layer formed on the substrate; a peel-off layer formed on the first flexible dielectric layer; and a unit to be peeled off formed on the peel-off layer; wherein an adhesive force between the peel-off layer and the first flexible dielectric layer is smaller than an adhesive force between the first flexible dielectric layer and the substrate, and the substrate, the first flexible dielectric layer, the peel-off layer, and the unit to be peeled off together form the multi-layer substrate structure. A method for manufacturing a multi-layer substrate structure which can be peeled off precisely is also provided.

Abstract: Various embodiments of the present application are directed towards a metal-insulator-metal (MIM) capacitor. The MIM capacitor comprises a bottom electrode disposed over a semiconductor substrate. A top electrode is disposed over and overlies the bottom electrode. A capacitor insulator structure is disposed between the bottom electrode and the top electrode. The capacitor insulator structure comprises at least three dielectric structures vertically stacked upon each other. A bottom half of the capacitor insulator structure is a mirror image of a top half of the capacitor insulator structure in terms of dielectric materials of the dielectric structures.

Abstract: Various embodiments of the present application are directed towards a method for forming a metal-insulator-metal (MIM) capacitor comprising an enhanced interfacial layer to reduce breakdown failure. In some embodiments, a bottom electrode layer is deposited over a substrate. A native oxide layer is formed on a top surface of the bottom electrode layer and has a first adhesion strength with the top surface. A plasma treatment process is performed to replace the native oxide layer with an interfacial layer. The interfacial layer is conductive and has a second adhesion strength with the top surface of the bottom electrode layer, and the second adhesion strength is greater than the first adhesion strength. An insulator layer is deposited on the interfacial layer. A top electrode layer is deposited on the insulator layer. The top and bottom electrode layers, the insulator layer, and the interfacial layer are patterned to form a MIM capacitor.

Abstract: In accordance with some embodiments, a method for processing semiconductor wafer is provided. The method includes loading a semiconductor wafer into a chamber. The method also includes creating an exhaust flow from the chamber. The method further includes depositing a film on the semiconductor wafer by supplying a processing gas into the chamber. In addition, the method includes detecting, with a use of a gas sensor, a concentration of the processing gas in the exhaust flow and generating a detection signal according to a result of the detection. The method further includes supplying a cleaning gas into the processing chamber for a time period after the film is formed on the semiconductor wafer. The time period is determined based on the detection signal.

Abstract: Various embodiments of the present disclosure are directed towards a three-dimensional (3D) trench capacitor, as well as methods for forming the same. In some embodiments, a first substrate overlies a second substrate so a front side of the first substrate faces a front side of the second substrate. A first trench capacitor and a second trench capacitor extend respectively into the front sides of the first and second substrates. A plurality of wires and a plurality of vias are stacked between and electrically coupled to the first and second trench capacitors. A first through substrate via (TSV) extends through the first substrate from a back side of the first substrate, and the wires and the vias electrically couple the first TSV to the first and second trench capacitors. The first and second trench capacitors and the electrical coupling therebetween collectively define the 3D trench capacitor.

Abstract: There is disclosed patient derived xenograft (PDXs) cells/systems/models and/or derivatives, parental (unlabelled) and/or labelled, expressing a fluorescent protein or a luciferase, or a combination thereof; for evaluating therapies comprising nasopharyngeal carcinoma (EBV positive and/or EBV negative). In another embodiment, there is disclosed a method of evaluating the efficacy of an agent used to treat nasopharyngeal carcinoma (NPC) comprising: preparing a non-human model; whereby the non-human model carries cells from NPC xenograft; labelling the cells from the NPC xenograft with gfp-luc2 marker using a lentiviral vector system; and growing the cells in short term in vitro culture; including adaptation of said culture into multi-well plates for use in further screening and/or evaluation assays; wherein the NPC xenograft is PDX.

Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.

Abstract: A scroll mouse includes a casing, a scroll wheel mouse and a waterproof module. The casing includes a first opening and a second opening. The scroll wheel includes a first rotation shaft and a second rotation shaft. The waterproof module includes a waterproof cap and a waterproof ring. A first gap between the first rotation shaft and the first opening is sealed by the waterproof cap. A second gap between the second rotation shaft and the second opening is sealed by the waterproof ring. Since the foreign liquid is prevented from entering an inner portion of the casing, the scroll mouse has the waterproof function.