Abstract: A heat dissipation device includes a base having a first surface in contact with at least one heat source and an opposite second surface having a heat dissipation zone upward extended therefrom; an auxiliary heat dissipation zone horizontally extended from one of four lateral sides or directions of the heat dissipation zone; an air guiding section defined at the auxiliary heat dissipation zone; and at least one upward indented zone formed between the auxiliary heat dissipation zone and the side of the heat dissipation zone having the auxiliary heat dissipation zone sideward sidewardly extended from a higher portion thereof. With these arrangements, the heat dissipation device can guide air flow currents directly or indirectly to a plurality of heat sources located corresponding to the heat dissipation zone and the auxiliary heat dissipation zone at the same time to cool them.

Abstract: The present disclosure relates to an image sensor comprising a substrate. A photodetector is in the substrate. A trench is in the substrate and is defined by sidewalls and an upper surface of the substrate. A first isolation layer extends along the sidewalls and the upper surface of the substrate that define the trench. The first isolation layer comprises a first dielectric material. A second isolation layer is over the first isolation layer. The second isolation layer lines the first isolation layer. The second isolation layer comprises a second dielectric material. A third isolation layer is over the second isolation layer. The third isolation layer fills the trench and lines the second isolation layer. The third isolation layer comprises a third material. A ratio of a first thickness of the first isolation layer to a second thickness of the second isolation layer is about 0.17 to 0.38.

Abstract: Various embodiments of the present disclosure are directed towards a three-dimensional (3D) trench capacitor, as well as methods for forming the same. In some embodiments, a first substrate overlies a second substrate so a front side of the first substrate faces a front side of the second substrate. A first trench capacitor and a second trench capacitor extend respectively into the front sides of the first and second substrates. A plurality of wires and a plurality of vias are stacked between and electrically coupled to the first and second trench capacitors. A first through substrate via (TSV) extends through the first substrate from a back side of the first substrate, and the wires and the vias electrically couple the first TSV to the first and second trench capacitors. The first and second trench capacitors and the electrical coupling therebetween collectively define the 3D trench capacitor.

Abstract: A multi-layer substrate structure which can be peeled off precisely includes: a substrate; a first flexible dielectric layer formed on the substrate; a peel-off layer formed on the first flexible dielectric layer; and a unit to be peeled off formed on the peel-off layer; wherein an adhesive force between the peel-off layer and the first flexible dielectric layer is smaller than an adhesive force between the first flexible dielectric layer and the substrate, and the substrate, the first flexible dielectric layer, the peel-off layer, and the unit to be peeled off together form the multi-layer substrate structure. A method for manufacturing a multi-layer substrate structure which can be peeled off precisely is also provided.

Abstract: Various embodiments of the present application are directed towards a metal-insulator-metal (MIM) capacitor. The MIM capacitor comprises a bottom electrode disposed over a semiconductor substrate. A top electrode is disposed over and overlies the bottom electrode. A capacitor insulator structure is disposed between the bottom electrode and the top electrode. The capacitor insulator structure comprises at least three dielectric structures vertically stacked upon each other. A bottom half of the capacitor insulator structure is a mirror image of a top half of the capacitor insulator structure in terms of dielectric materials of the dielectric structures.

Abstract: Various embodiments of the present application are directed towards a method for forming a metal-insulator-metal (MIM) capacitor comprising an enhanced interfacial layer to reduce breakdown failure. In some embodiments, a bottom electrode layer is deposited over a substrate. A native oxide layer is formed on a top surface of the bottom electrode layer and has a first adhesion strength with the top surface. A plasma treatment process is performed to replace the native oxide layer with an interfacial layer. The interfacial layer is conductive and has a second adhesion strength with the top surface of the bottom electrode layer, and the second adhesion strength is greater than the first adhesion strength. An insulator layer is deposited on the interfacial layer. A top electrode layer is deposited on the insulator layer. The top and bottom electrode layers, the insulator layer, and the interfacial layer are patterned to form a MIM capacitor.

Abstract: In accordance with some embodiments, a method for processing semiconductor wafer is provided. The method includes loading a semiconductor wafer into a chamber. The method also includes creating an exhaust flow from the chamber. The method further includes depositing a film on the semiconductor wafer by supplying a processing gas into the chamber. In addition, the method includes detecting, with a use of a gas sensor, a concentration of the processing gas in the exhaust flow and generating a detection signal according to a result of the detection. The method further includes supplying a cleaning gas into the processing chamber for a time period after the film is formed on the semiconductor wafer. The time period is determined based on the detection signal.

Abstract: Various embodiments of the present disclosure are directed towards a three-dimensional (3D) trench capacitor, as well as methods for forming the same. In some embodiments, a first substrate overlies a second substrate so a front side of the first substrate faces a front side of the second substrate. A first trench capacitor and a second trench capacitor extend respectively into the front sides of the first and second substrates. A plurality of wires and a plurality of vias are stacked between and electrically coupled to the first and second trench capacitors. A first through substrate via (TSV) extends through the first substrate from a back side of the first substrate, and the wires and the vias electrically couple the first TSV to the first and second trench capacitors. The first and second trench capacitors and the electrical coupling therebetween collectively define the 3D trench capacitor.

Abstract: There is disclosed patient derived xenograft (PDXs) cells/systems/models and/or derivatives, parental (unlabelled) and/or labelled, expressing a fluorescent protein or a luciferase, or a combination thereof; for evaluating therapies comprising nasopharyngeal carcinoma (EBV positive and/or EBV negative). In another embodiment, there is disclosed a method of evaluating the efficacy of an agent used to treat nasopharyngeal carcinoma (NPC) comprising: preparing a non-human model; whereby the non-human model carries cells from NPC xenograft; labelling the cells from the NPC xenograft with gfp-luc2 marker using a lentiviral vector system; and growing the cells in short term in vitro culture; including adaptation of said culture into multi-well plates for use in further screening and/or evaluation assays; wherein the NPC xenograft is PDX.

Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.

Abstract: A scroll mouse includes a casing, a scroll wheel mouse and a waterproof module. The casing includes a first opening and a second opening. The scroll wheel includes a first rotation shaft and a second rotation shaft. The waterproof module includes a waterproof cap and a waterproof ring. A first gap between the first rotation shaft and the first opening is sealed by the waterproof cap. A second gap between the second rotation shaft and the second opening is sealed by the waterproof ring. Since the foreign liquid is prevented from entering an inner portion of the casing, the scroll mouse has the waterproof function.

Abstract: A roller mouse includes a casing, a wheel module, a swingable assembly and an adjusting element. The wheel module includes a wheel element. The swingable assembly is fixed on the wheel module, and located near the wheel element. When the adjusting element is in a first position, the swingable assembly is contacted with the wheel element, so that the wheel module is in a first clicking mode. When the adjusting element is moved to a second position, the swingable assembly is pushed by the adjusting element, and the swingable assembly is separated from the wheel element, so that the wheel module is in a second clicking mode.

Abstract: A method includes providing a first design layout including cells; updating a first cell in the plurality of cells using optical proximity correction to provide a first updated cell and a data set; training a model based on a layout-dependent parameter of a second design layout; and updating a second cell based on the data set and the model to provide a second updated cell. The model includes an input layer, a hidden layer and an output layer. Training the model includes obtaining converged values of nodes of the hidden layer. Obtaining converged values of nodes of the hidden layer includes providing information on edge segments before and after lithography enhancement to the input layer and the output layer, respectively, until values of nodes of the hidden layer attains convergence in terms of a cost function.

Abstract: A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.

Abstract: Various embodiments of the present application are directed towards a method for forming a metal-insulator-metal (MIM) capacitor comprising an enhanced interfacial layer to reduce breakdown failure. In some embodiments, a bottom electrode layer is deposited over a substrate. A native oxide layer is formed on a top surface of the bottom electrode layer and has a first adhesion strength with the top surface. A plasma treatment process is performed to replace the native oxide layer with an interfacial layer. The interfacial layer is conductive and has a second adhesion strength with the top surface of the bottom electrode layer, and the second adhesion strength is greater than the first adhesion strength. An insulator layer is deposited on the interfacial layer. A top electrode layer is deposited on the insulator layer. The top and bottom electrode layers, the insulator layer, and the interfacial layer are patterned to form a MIM capacitor.

Abstract: Various embodiments of the present disclosure are directed towards a three-dimensional (3D) trench capacitor, as well as methods for forming the same. In some embodiments, a first substrate overlies a second substrate so a front side of the first substrate faces a front side of the second substrate. A first trench capacitor and a second trench capacitor extend respectively into the front sides of the first and second substrates. A plurality of wires and a plurality of vias are stacked between and electrically coupled to the first and second trench capacitors. A first through substrate via (TSV) extends through the first substrate from a back side of the first substrate, and the wires and the vias electrically couple the first TSV to the first and second trench capacitors. The first and second trench capacitors and the electrical coupling therebetween collectively define the 3D trench capacitor.

Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.

Abstract: In accordance with some embodiments, a method for processing semiconductor wafer is provided. The method includes loading a semiconductor wafer into a chamber. The method also includes creating an exhaust flow from the chamber. The method further includes depositing a film on the semiconductor wafer by supplying a processing gas into the chamber. In addition, the method includes detecting, with a use of a gas sensor, a concentration of the processing gas in the exhaust flow and generating a detection signal according to a result of the detection. The method further includes supplying a cleaning gas into the processing chamber for a time period after the film is formed on the semiconductor wafer. The time period is determined based on the detection signal.

Abstract: A method and a system of performing layout enhancement include: providing a first design layout comprising a plurality of cells; updating a first cell in the plurality of cells using optical proximity correction to provide a first updated cell and a data set; updating a second cell from remaining cells in the first design layout based on the data set to provide a second updated cell; and manufacturing a mask based on the first updated cell and the second updated cell in the first design layout.

Abstract: A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.