Abstract: A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.

Abstract: Disclosed are a binder and a battery including the binder. The novel aqueous binder with self cross-linking performance, strong bonding performance, and good flexibility is obtained by copolymerizing a plurality of functional monomers. The binder has the characteristics of good processability and high solid content of the slurry when applied to a positive electrode; the positive electrode plate obtained by applying the slurry has high peeling force and good cyclic stability, and its rate capability is superior to that obtained by applying PVDF binder; and the binder is green and environmental friendly, and it is expected to replace PVDF in batteries and achieve large-scale application.

Abstract: The present disclosure relates to an image sensor comprising a substrate. A photodetector is in the substrate. A trench is in the substrate and is defined by sidewalls and an upper surface of the substrate. A first isolation layer extends along the sidewalls and the upper surface of the substrate that define the trench. The first isolation layer comprises a first dielectric material. A second isolation layer is over the first isolation layer. The second isolation layer lines the first isolation layer. The second isolation layer comprises a second dielectric material. A third isolation layer is over the second isolation layer. The third isolation layer fills the trench and lines the second isolation layer. The third isolation layer comprises a third material. A ratio of a first thickness of the first isolation layer to a second thickness of the second isolation layer is about 0.17 to 0.38.

Abstract: In an integrated circuit (IC) fabrication process, devices or sub-circuits are fabricated in respective first and second electrical isolation regions. A back-to-back (B2B) diodes sub-circuit is fabricated in a third electrical isolation region, which includes a first diode whose cathode is connected with a first terminal and whose anode is connected with a second terminal, and a second diode whose anode is connected with the first terminal and whose cathode is connected with the second terminal. Electrostatic discharge protection is provided to the first and second electrical isolation regions by electrically connecting the first terminal of the B2B diodes sub-circuit with a VSS power supply terminal of the first device or sub-circuit and the second terminal of the B2B diodes sub-circuit with a VSS power supply terminal of the second device or sub-circuit. Thereafter, the first device or sub-circuit and the second device or sub-circuit are electrically connected.

Abstract: A method includes providing a first design layout including cells; updating a first cell in the plurality of cells using optical proximity correction to provide a first updated cell and a data set; training a model based on a layout-dependent parameter of a second design layout; and updating a second cell based on the data set and the model to provide a second updated cell. The model includes an input layer, a hidden layer and an output layer. Training the model includes obtaining converged values of nodes of the hidden layer. Obtaining converged values of nodes of the hidden layer includes providing information on edge segments before and after lithography enhancement to the input layer and the output layer, respectively, until values of nodes of the hidden layer attains convergence in terms of a cost function.

Abstract: An electronic device assembly includes a first electronic device and a second electronic device. The first electronic device includes a first wall body, a first opening, a sliding seat, a first magnetic attraction element, an elastic element and a connecting terminal. When the second wall body is close to the first wall body, the second magnetic attraction element and the first magnetic attraction element are magnetically attracted by each other. Consequently, the sliding seat is moved toward the first wall body, the elastic element is compressed, and the connecting terminal is protruded outside the first opening and contacted with the connector. When the second wall body is separated from the first wall body, the compressed elastic element is restored. Consequently, the sliding seat is moved away from the first wall body and the connecting terminal is retracted inside the first electronic device.

Abstract: A mouse device includes a wheel control mechanism and a control unit. The control unit is electrically connected with a magnetic force module and a rotating speed detector of the wheel control mechanism. Under control of the control unit, a first direction current or a second direction current is selectively provided to drive the magnetic force module. The flowing directions of the first direction current and the second direction current are opposite. Consequently, the rotating mode of the wheel control mechanism can be switched between different modes.

Abstract: Various embodiments of the present application are directed towards a method for forming a metal-insulator-metal (MIM) capacitor comprising an enhanced interfacial layer to reduce breakdown failure. In some embodiments, a bottom electrode layer is deposited over a substrate. A native oxide layer is formed on a top surface of the bottom electrode layer and has a first adhesion strength with the top surface. A plasma treatment process is performed to replace the native oxide layer with an interfacial layer. The interfacial layer is conductive and has a second adhesion strength with the top surface of the bottom electrode layer, and the second adhesion strength is greater than the first adhesion strength. An insulator layer is deposited on the interfacial layer. A top electrode layer is deposited on the insulator layer. The top and bottom electrode layers, the insulator layer, and the interfacial layer are patterned to form a MIM capacitor.

Abstract: Pharmaceutical preparations containing polypeptides having particular sialylation patterns, and methods for the treatment of immune-related thrombocytopenia with such preparations, are described.

Abstract: In an integrated circuit (IC) fabrication process, devices or sub-circuits are fabricated in respective first and second electrical isolation regions. A back-to-back (B2B) diodes sub-circuit is fabricated in a third electrical isolation region, which includes a first diode whose cathode is connected with a first terminal and whose anode is connected with a second terminal, and a second diode whose anode is connected with the first terminal and whose cathode is connected with the second terminal. Electrostatic discharge protection is provided to the first and second electrical isolation regions by electrically connecting the first terminal of the B2B diodes sub-circuit with a VSS power supply terminal of the first device or sub-circuit and the second terminal of the B2B diodes sub-circuit with a VSS power supply terminal of the second device or sub-circuit. Thereafter, the first device or sub-circuit and the second device or sub-circuit are electrically connected.

Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.

Abstract: Disclosed are a negative electrode plate and a battery. A first negative active material layer is disposed at a bottom layer, and includes a first binder resistant to electrolyte swelling, has a better chemical corrosion resistance, and is not easy to age, so as to ensure long-term bonding, and reduce battery cell expansio. The negative electrode plate can maintain good mechanical strength and elongation at immersion of the electrolyte, so as to ensure that it is not separatedr. A second binder in a second negative active material layer away from the negative current collector uses a high swelling material, the high-swelling binder is in good affinity with the electrolyte, and the electrolyte infiltration speed is good, which facilitates lithium ion conduction. Furthermore, the high-swelling binder is bound to the separator well in a hot pressing process, so as to improve an interface bonding effect.

Abstract: Disclosed are a pre-lithiated silicon negative electrode material, a silicon negative electrode plate, a method for preparing the same, and a lithium-ion battery. The pre-lithiated silicon negative electrode material includes a silicon negative electrode material and a lithium-containing polymer compounded with the silicon negative electrode material. The lithium-containing polymer includes a polymer shown in the following formula 1, where x is 1 to 12, and R1 is I; or II, where y is 1 to 4; or III or IV. The use of the pre-lithiated silicon negative electrode material can improve performance, such as initial Coulombic efficiency, of a lithium-ion battery.

Abstract: Various embodiments of the present disclosure are directed towards an amorphous bottom electrode structure (BES) for a metal-insulator-metal (MIM) capacitor. The MIM capacitor comprises a bottom electrode, an insulator layer overlying the bottom electrode, and a top electrode overlying the insulator layer. The bottom electrode comprises a crystalline BES and the amorphous BES, and the amorphous BES overlies the crystalline BES and forms a top surface of the bottom electrode. Because the amorphous BES is amorphous, instead of crystalline, a top surface of the amorphous BES may have a small roughness compared to that of the crystalline BES. Because the amorphous BES forms the top surface of the bottom electrode, the top surface of the bottom electrode may have a small roughness compared to what it would otherwise have if the crystalline BES formed the top surface. The small roughness may improve a lifespan of the MIM capacitor.

Abstract: Various embodiments of the present application are directed towards a method for forming a metal-insulator-metal (MIM) capacitor comprising an enhanced interfacial layer to reduce breakdown failure. In some embodiments, a bottom electrode layer is deposited over a substrate. A native oxide layer is formed on a top surface of the bottom electrode layer and has a first adhesion strength with the top surface. A plasma treatment process is performed to replace the native oxide layer with an interfacial layer. The interfacial layer is conductive and has a second adhesion strength with the top surface of the bottom electrode layer, and the second adhesion strength is greater than the first adhesion strength. An insulator layer is deposited on the interfacial layer. A top electrode layer is deposited on the insulator layer. The top and bottom electrode layers, the insulator layer, and the interfacial layer are patterned to form a MIM capacitor.

Abstract: A liquid-crystal polymer includes at least one repeating unit having a spiro structure, and the repeating unit occupies 1 mol % to 20 mol % of the liquid-crystal polymer. The liquid-crystal polymer is composed of the following repeating units: 1 mol % to 20 mol % of 10 mol % to 35 mol % of 10 mol % to 35 mol % of 10 mol % to 50 mol % of and 10 mol % to 40 mol % of AR1 is wherein each of ring R and ring S is independently a C3-20 ring, ring R and ring S share a carbon atom, and each of K1 and K2 is independently a C5-20 conjugated system. Each of AR2, AR3, AR4, and AR5 is independently AR6 or AR6—Z—AR7.

Abstract: According to an aspect, an image sensor package includes a substrate, an image sensor die coupled to the substrate, and a transparent member including a first surface and a second surface, where the second surface of the transparent member is coupled to the image sensor die via one or more dam members such that an empty space exists between an active area of the image sensor die and the second surface of the transparent member. The image sensor package includes a light blocking member coupled to or defined by the transparent member.

Abstract: A heat dissipation device includes a base having a first surface in contact with at least one heat source and an opposite second surface having a heat dissipation zone upward extended therefrom; an auxiliary heat dissipation zone horizontally extended from one of four lateral sides or directions of the heat dissipation zone; an air guiding section defined at the auxiliary heat dissipation zone; and at least one upward indented zone formed between the auxiliary heat dissipation zone and the side of the heat dissipation zone having the auxiliary heat dissipation zone sideward sidewardly extended from a higher portion thereof. With these arrangements, the heat dissipation device can guide air flow currents directly or indirectly to a plurality of heat sources located corresponding to the heat dissipation zone and the auxiliary heat dissipation zone at the same time to cool them.

Abstract: A method of detecting or monitoring process electrical charge produced during fabrication of an integrated circuit (IC) on a semiconductor wafer includes fabricating a process charge detection circuit on or in the semiconductor wafer, including: a victim isolation well, a gate oxide disposed on or in the victim isolation well, an aggressor isolation well electrically connected with the victim isolation well via the gate oxide, a victim antenna electrically connected with the victim isolation well and together with the victim isolation well defining a victim RC time constant, and an aggressor antenna electrically connected with the aggressor isolation well and together with the aggressor isolation well defining an aggressor RC time constant that is different from the victim RC time constant. Process charge is detected using the process charge detection circuit. The detecting comprises measuring an electrical parameter of the gate oxide.

Abstract: The present invention relates to pegylated amino acid compounds of Formula I: and pharmaceutically acceptable salts thereof, wherein X, R1, R2, R3A, R3B and n are as defined herein. The present invention also relates to compositions which comprise a pegylated amino acid compound of the invention or a pharmaceutically acceptable salt thereof, and a pharmaceutically acceptable carrier, in combination with a high concentration of an active biological ingredient (ABI). In embodiments of the invention, the ABI is an anti-PD-1 antibody or antigen binding fragment thereof that specifically binds human programmed death receptor 1 (PD-1). The invention further relates to methods for lowering the viscosity of an aqueous solution of a pharmaceutical composition comprising adding a compound of the invention to the solution.