Abstract: A semiconductor device structure is provided. The device includes one or more first semiconductor layers, and a dipole layer surrounding each first semiconductor layer of the one or more first semiconductor layers, wherein the dipole layer comprises germanium. The structure also includes a capping layer surrounding and in contact with the dipole layer, wherein the capping layer comprises silicon, one or more second semiconductor layers disposed adjacent the one or more first semiconductor layers. The structure further includes a gate electrode layer surrounding each first semiconductor layer of the one or more first semiconductor layers and each second semiconductor layer of the one or more second semiconductor layers.

Abstract: An antenna system includes a signal feeding element, a first antenna element, a second antenna element, a first transmission line, and a second transmission line. The first antenna element is coupled to a first connection point. The second antenna element is coupled to a second connection point. The first transmission line is coupled between the signal feeding element and the first connection point. The second transmission line is coupled between the signal feeding element and the second connection point. The length of the second transmission line is substantially equal to that of the first transmission line. The first antenna element and the second antenna element substantially have opposite polarization directions. Therefore, the radiation pattern of the antenna system can provide a plurality of different gain peaks.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes placing a package substrate on a carrier substrate, forming a frame on the package substrate, and affixing an active side of a semiconductor die on the package substrate. The semiconductor die together with the frame and the package substrate form a cavity between the semiconductor die and the package substrate. At least a portion of the semiconductor die and the package substrate are encapsulated with an encapsulant. The frame is configured to prevent the encapsulant from entering the cavity.

Abstract: Provided are a marking information processing method and device, and a storage medium. The method includes receiving a marking information synchronization request and a first list sent by a client device; detecting the validity of the marking information synchronization request; and in the case where the marking information synchronization request passes validity detection, synchronizing the marking information corresponding to the marking information synchronization request to a second list corresponding to a target account. The marking information is obtained by the client device in response to a marking operation on a display object when the account is not logged in.

Abstract: A coring and sampling integrated sub, including an integrally formed base body, a probe module, a coring module and a hydraulic module. The probe module, the coring module and the hydraulic module are all mounted on the base body. The hydraulic module, the probe module and the coring module are sequentially arranged from top to bottom. An output end of the hydraulic module is configured to be connected to the probe module and the coring module, respectively. The hydraulic module is configured to provide telescopic power for the probe module, and provide power for movement, flipping, and pushing of the coring module. Also disclosed is a downhole instrument including the coring and sampling integrated sub.

Abstract: Antibodies that include an antigen binding region that binds to CD137 are provided herein. Also provided herein are bispecific antibodies that include a first antigen binding region that binds to CD137 and a second antigen binding region that binds to an immune checkpoint molecule, an immune stimulatory molecule, or a tumor antigen. Pharmaceutical compositions that include the antibodies and methods of treating cancer are provided.

Abstract: A heat transmitting device is provided, including a main body and an integrating portion. The main body has at least one opening. The integrating portion is used to seal the opening, and has a first surface and a second surface opposite the first surface. A first welding pattern is formed on the first surface, a second welding pattern is formed on the second surface, and the position of the first welding pattern corresponds to that of the second welding pattern. The type of the first welding pattern and the type of the second welding pattern are asymmetric.

Abstract: An optical camera lens assembly is provided, including: a lens group, including a first lens, a second lens, a third lens, a fourth lens, a fifth lens, a sixth lens and a seventh lens arranged sequentially along an optical axis from an object side to an image side, where, each of the first, the fourth, and the sixth lens has a positive refractive power, and each of the second, the third, the fifth, and the seventh lens has a negative refractive power; and a plurality of spacing elements, including a third spacing element disposed between the third lens and the fourth lens and in contact with an image-side surface of the third lens; the optical camera lens assembly satisfies: 3.0<(R3+R4)/d3s<5.0.

Abstract: An electrical connector includes a socket, a plug and a locking component. The socket includes a socket case having a fixing groove disposed at the outer surface and a socket terminal configured in the socket case. The plug includes a plug case having a locking hole, a containing space configured for containing the socket case and a plug terminal configured in the containing space. The locking component is disposed in the locking hole and configured to move in the locking hole. When the plug is connected to the socket, the socket terminal embeds into the plug terminal, so that the socket case is located between the plug case and the plug terminal and the fixing groove is corresponding to the locking hole. Then, the locking component moves toward the plug terminal and engages to the fixing groove to lock the plug and the socket.

Abstract: A semiconductor device includes a substrate, a passing word line in the substrate, and a dielectric structure surrounding the passing word line. The dielectric structure has an enlargement portion at a bottom of the dielectric structure, and a maximum width of the enlargement portion of the dielectric structure is wider than a width of a top of the dielectric structure.

Abstract: A heat pipe comprises a flat tube and a wick structure. The flat tube includes a hollow chamber and has a front and a rear sealed ends along an axial direction. The wick structure is disposed in the hollow chamber and extended along the axial direction of the flat tube. The wick structure is divided into a front, a middle and a rear sections sequentially along the axial direction. The front section is near the front sealed end, the rear section is near the rear sealed end. The front, middle and rear sections have a maximum length parallel to the width direction, respectively. The maximum length of the front section is greater than that of the middle section, and the maximum length of the middle section is greater than that of the rear section.

Abstract: The present disclosure describes a semiconductor device having an isolation structure. The semiconductor structure includes a set of nanostructures on a substrate, a gate dielectric layer wrapped around the set of nanostructures, a work function metal layer on the gate dielectric layer and around the set of nanostructures, and the isolation structure adjacent to the set of nanostructures and in contact with the work function metal layer. A portion of the work function metal layer is on a top surface of the isolation structure.

Abstract: A method for processing an integrated circuit includes forming I/O gate all around transistors and core gate all around transistors. The method performs a regrowth process on an interfacial dielectric layer of the I/O gate all around transistors by diffusing metal atoms into the interfacial dielectric layer of the I/O gate all around transistor. The regrowth process does not diffuse metal atoms into the interfacial gate dielectric layer of the core gate all around transistor.

Abstract: A method of manufacturing a panel assembly includes supporting the panel assembly in a free state using a holding fixture. The panel assembly has a skin panel, and sacrificial material coupled to a skin panel inner surface. The method includes acquiring a free state outer surface contour of the panel assembly by scanning a skin panel outer surface while the panel assembly is supported by the holding fixture. The method also includes developing a numerically controlled (NC) machining program having cutter paths configured for machining the interface locations to an inner surface contour that reflects nominal thicknesses of the panel assembly based off of the free state outer surface contour. In addition, the method includes machining the sacrificial material at the interface locations by moving a cutter along the cutter paths while the panel assembly is supported by the holding fixture.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first transistor having a first conductivity type arranged over a substrate. The first transistor includes a first gate electrode layer having a first work function and extending from a first source/drain region to a second source/drain region, and a first channel structure embedded in the first gate electrode layer and extending from the first source/drain region to the second source/drain region. A second transistor having the first conductivity type is arranged laterally beside the first transistor. The second transistor includes a second gate electrode layer having a second work function that is different than the first work function and extending from a third source/drain region to a fourth source/drain region. A second channel structure is embedded in the second gate electrode layer and extends from the third source/drain region to the fourth source/drain region.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.

Abstract: An antenna system with switchable radiation gain includes a signal feeding element, a first antenna element, a second antenna element, a first diode, a first switch element, a second switch element, a first impedance transformer, and a second impedance transformer. The first antenna element is coupled to a first connection point. The second antenna element is coupled to a second connection point. The first diode has an anode coupled to the first connection point, and a cathode coupled to the second connection point. The first switch element and the second switch element are configured to select either the first impedance transformer or the second impedance transformer as a first target transformer, and the selected first target transformer is coupled between the first connection point and the signal feeding element.

Abstract: The present disclosure provides a method for a display driver system and a display driver system.

Abstract: Some embodiment structures and methods are described. A structure includes an integrated circuit die at least laterally encapsulated by an encapsulant, and a redistribution structure on the integrated circuit die and encapsulant. The redistribution structure is electrically coupled to the integrated circuit die. The redistribution structure includes a first dielectric layer on at least the encapsulant, a metallization pattern on the first dielectric layer, a metal oxide layered structure on the metallization pattern, and a second dielectric layer on the first dielectric layer and the metallization pattern. The metal oxide layered structure includes a metal oxide layer having a ratio of metal atoms to oxygen atoms that is substantially 1:1, and a thickness of the metal oxide layered structure is at least 50 ?. The second dielectric layer is a photo-sensitive material. The metal oxide layered structure is disposed between the metallization pattern and the second dielectric layer.