Abstract: A chip package structure is provided. The chip package structure includes a first substrate. The chip package structure includes a conductive via structure passing through the first substrate. The chip package structure includes a barrier layer over a surface of the first substrate. The chip package structure includes an insulating layer over the barrier layer. The chip package structure includes a conductive pad over the insulating layer and having a first portion and a second portion. The chip package structure includes a conductive bump over the second portion of the conductive pad. A third portion of the conductive pad is between the conductive bump and the conductive via structure from a top view of the conductive pad, the conductive bump, and the conductive via structure.

Abstract: A semiconductor device includes a first channel region disposed in a first device region over a substrate; a first gate dielectric layer disposed over the first channel region; a second gate dielectric layer disposed over the second channel region; and a gate electrode disposed over the first gate dielectric layer. The first gate dielectric layer includes a first dipole dopant and the second gate dielectric layer includes a second dipole dopant embedded therein. A boundary between the first gate dielectric layer and the second gat dielectric layer contains the first dipole dopant and the second dipole dopant.

Abstract: An intelligent auxiliary gout diagnosis and treatment system for combination of traditional Chinese medicine and western medicine includes a knowledge extraction module, a predictive reasoning module, an evaluation feedback module and a data storage module. The knowledge extraction module is configured to construct a gout knowledge graph. The predictive reasoning module is configured to learn a predictive model in combination with historical annotation data to perform reasoning diagnosis, predict a gout course stage of a patient and recommend a treatment plan. The evaluation feedback module is configured to evaluate a diagnosis and treatment effect for strengthening the system and improving an intelligent level of the system. The data storage module is configured to store data of the system.

Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive bump over and electrically connected to the chip. The chip package structure includes a ring-like structure over and electrically insulated from the chip. The ring-like structure surrounds the conductive bump, and the ring-like structure and the conductive bump are made of a same material.

Abstract: The present disclosure discloses an optical imaging lens assembly including, sequentially from an object side to an image side along an optical axis, a first lens, a second lens, a third lens, a fourth lens, a fifth lens, and a sixth lens. The first lens has a positive refractive power, both of an object-side surface and an image-side surface thereof are convex surfaces; the second lens has a negative refractive power; the third lens has a negative refractive power, and an image-side surface thereof is a concave surface; the fourth lens has a refractive power; the fifth lens has a refractive power, and an image-side surface thereof is a convex surface; the sixth lens has a refractive power, and an object-side surface thereof is a concave surface. Half of a maximal field-of-view HFOV of the optical imaging lens assembly satisfies HFOV<30°.

Abstract: A semiconductor having a first gate-all-around (GAA) transistor, a second GAA transistor, and a third GAA transistor is provided. The first (GAA) transistor includes a first plurality of channel members, a gate dielectric layer over the first plurality of channel members, a first work function layer over the gate dielectric layer, and a glue layer over the first work function layer. The second GAA transistor include a second plurality of channel members, the gate dielectric layer over the second plurality of channel members, and a second work function layer over the gate dielectric layer, the first work function layer over and in contact with the second work function layer, and the glue layer over the first work function layer. The third GAA transistor includes a third plurality of channel members, the gate dielectric layer over the third plurality of channel members, and the glue layer over the gate dielectric layer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor layers and second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers are separated and stacked up, and a thickness of each second semiconductor layer is less than a thickness of each first semiconductor layer; a first interfacial layer around each first semiconductor layer; a second interfacial layer around each second semiconductor layer; a first dipole gate dielectric layer around each first semiconductor layer and over the first interfacial layer; a second dipole gate dielectric layer around each second semiconductor layer and over the second interfacial layer; a first gate electrode around each first semiconductor layer and over the first dipole gate dielectric layer; and a second gate electrode around each second semiconductor layer and over the second dipole gate dielectric layer.

Abstract: A memory device includes a substrate, a spin-orbit torque (SOT) layer, a magnetic tunneling junction (MTJ) film stack, a connecting via and a shielding structure. The SOT layer is disposed on the substrate. The MTJ film stack is formed over SOT layer and on the substrate. The connecting via is disposed on and electrically connected to the MTJ film stack. The shielding structure is laterally surrounding the MTJ film stack and disposed on the SOT layer, wherein the shielding structure includes a first dielectric layer, a high magnetic permeability layer and a second dielectric layer, the first dielectric layer is in contact with the SOT layer and the MTJ film stack, and the high magnetic permeability layer is sandwiched between the first dielectric layer and the second dielectric layer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor layers and second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers are separated and stacked up, and a thickness of each second semiconductor layer is less than a thickness of each first semiconductor layer; a first interfacial layer around each first semiconductor layer; a second interfacial layer around each second semiconductor layer; a first dipole gate dielectric layer around each first semiconductor layer and over the first interfacial layer; a second dipole gate dielectric layer around each second semiconductor layer and over the second interfacial layer; a first gate electrode around each first semiconductor layer and over the first dipole gate dielectric layer; and a second gate electrode around each second semiconductor layer and over the second dipole gate dielectric layer.

Abstract: A structure has stacks of semiconductor layers over a substrate and adjacent a dielectric feature. A gate dielectric is formed wrapping around each layer and the dielectric feature. A first layer of first gate electrode material is deposited over the gate dielectric and the dielectric feature. The first layer on the dielectric feature is recessed to a first height below a top surface of the dielectric feature. A second layer of the first gate electrode material is deposited over the first layer. The first gate electrode material in a first region of the substrate is removed to expose a portion of the gate dielectric in the first region, while the first gate electrode material in a second region of the substrate is preserved. A second gate electrode material is deposited over the exposed portion of the gate dielectric and over a remaining portion of the first gate electrode material.

Abstract: A semiconductor device structure is provided. The device includes one or more first semiconductor layers, and a dipole layer surrounding each first semiconductor layer of the one or more first semiconductor layers, wherein the dipole layer comprises germanium. The structure also includes a capping layer surrounding and in contact with the dipole layer, wherein the capping layer comprises silicon, one or more second semiconductor layers disposed adjacent the one or more first semiconductor layers. The structure further includes a gate electrode layer surrounding each first semiconductor layer of the one or more first semiconductor layers and each second semiconductor layer of the one or more second semiconductor layers.

Abstract: A method includes etching a first recess adjacent a first dummy gate stack and a first fin; etching a second recess adjacent a second dummy gate stack and a second fin; and epitaxially growing a first epitaxy region in the first recess. The method further includes depositing a first metal-comprising mask over the first dummy gate stack, over the second dummy gate stack, over the first epitaxy region in the first recess, and in the second recess; patterning the first metal-comprising mask to expose the first dummy gate stack and the first epitaxy region; epitaxially growing a second epitaxy region in the first recess over the first epitaxy region; and after epitaxially growing the second epitaxy region, removing remaining portions of the first metal-comprising mask.

Abstract: An LED backlight driver includes at least one driving chip configured to drive a backlight module. The at least one driving chip is disposed on at least one chip-on-film package, and not in direct contact with the backlight module to reduce heat transfer to the backlight module.

Abstract: A package structure includes a first semiconductor die having a first conductive pad and a second semiconductor die having a second conductive pad. The package structure also includes a conductive structure and a third semiconductor die. The third semiconductor die extends across a portions of the first semiconductor die and the second semiconductor die. A third conductive pad and a fourth conductive pad of the third semiconductor die are aligned with the first conductive pad and the second conductive pad, respectively. The package structure further includes a protective layer surrounding the conductive structure and the third semiconductor die and an insulating layer extending across an interface between the protective layer and the conductive structure. The package structure includes a conductive layer electrically connected to the conductive structure. The conductive layer has a first portion spaced from the conductive structure and a second portion directly above the conductive structure.

Abstract: An antenna system includes a signal feeding element, a first antenna element, a second antenna element, a first selection circuit, a second selection circuit, a first transmission line, a second transmission line, a third transmission line, a fourth transmission line, a fifth transmission line, and a sixth transmission line. The first selection circuit selects one of the first transmission line, the second transmission line, and the third transmission line as a first target transmission line. The selected first target transmission line is coupled between a third connection point and a first connection point. The second selection circuit selects one of the fourth transmission line, the fifth transmission line, and the sixth transmission line as a second target transmission line. The selected second target transmission line is coupled between a fourth connection point and a second connection point.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes first and second dielectric features and a first semiconductor layer disposed between the first and second dielectric features. The structure further includes an isolation layer disposed between the first and second dielectric features, and the isolation layer is in contact with the first and second dielectric features. The first semiconductor layer is disposed over the isolation layer. The structure further includes a gate dielectric layer disposed over the isolation layer and a gate electrode layer disposed over the gate dielectric layer. The gate electrode layer has an end extending to a level between a first plane defined by a first surface of the first semiconductor layer and a second plane defined by a second surface opposite the first surface.

Abstract: A memory device is provided. The memory device includes a substrate, a spin-orbit torque layer and a magnetic tunneling junction (MTJ). The MTJ stacks with the spin-orbit torque layer over the substrate and includes a synthetic free layer, a barrier layer and a reference layer. The synthetic free layer includes a synthetic antiferromagnetic structure, a first spacer layer and a free layer, wherein the synthetic antiferromagnetic structure is disposed between the spin-orbit torque layer and the free layer. The barrier layer is disposed beside the synthetic free layer. The reference layer is disposed beside the barrier layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a magnetic element over the substrate. The semiconductor device structure also includes an isolation element partially covering the magnetic element. The semiconductor device structure further includes a conductive feature over the isolation element.

Abstract: A memory device including a pair of magnetic conductive posts, a Spin-Hall-Effect-assisted (SHE-assisted) layer, and a magnetic tunneling junction (MTJ) structure. The Spin-Hall-Effect-assisted (SHE-assisted) layer is disposed over and electrically connected to the pair of magnetic conductive posts. The magnetic tunneling junction (MTJ) structure has in-plane magnetic anisotropy, wherein the MTJ structure is disposed on the SHE-assisted layer, and the pair of magnetic conductive posts provide an in-plane magnetic field during a write operation of the MTJ structure.