Abstract: An electrical connector includes a socket, a plug and a locking component. The socket includes a socket case having a fixing groove disposed at the outer surface and a socket terminal configured in the socket case. The plug includes a plug case having a locking hole, a containing space configured for containing the socket case and a plug terminal configured in the containing space. The locking component is disposed in the locking hole and configured to move in the locking hole. When the plug is connected to the socket, the socket terminal embeds into the plug terminal, so that the socket case is located between the plug case and the plug terminal and the fixing groove is corresponding to the locking hole. Then, the locking component moves toward the plug terminal and engages to the fixing groove to lock the plug and the socket.

Abstract: The present disclosure describes a semiconductor device having an isolation structure. The semiconductor structure includes a set of nanostructures on a substrate, a gate dielectric layer wrapped around the set of nanostructures, a work function metal layer on the gate dielectric layer and around the set of nanostructures, and the isolation structure adjacent to the set of nanostructures and in contact with the work function metal layer. A portion of the work function metal layer is on a top surface of the isolation structure.

Abstract: A semiconductor device includes a substrate, a passing word line in the substrate, and a dielectric structure surrounding the passing word line. The dielectric structure has an enlargement portion at a bottom of the dielectric structure, and a maximum width of the enlargement portion of the dielectric structure is wider than a width of a top of the dielectric structure.

Abstract: A heat pipe comprises a flat tube and a wick structure. The flat tube includes a hollow chamber and has a front and a rear sealed ends along an axial direction. The wick structure is disposed in the hollow chamber and extended along the axial direction of the flat tube. The wick structure is divided into a front, a middle and a rear sections sequentially along the axial direction. The front section is near the front sealed end, the rear section is near the rear sealed end. The front, middle and rear sections have a maximum length parallel to the width direction, respectively. The maximum length of the front section is greater than that of the middle section, and the maximum length of the middle section is greater than that of the rear section.

Abstract: A method for processing an integrated circuit includes forming I/O gate all around transistors and core gate all around transistors. The method performs a regrowth process on an interfacial dielectric layer of the I/O gate all around transistors by diffusing metal atoms into the interfacial dielectric layer of the I/O gate all around transistor. The regrowth process does not diffuse metal atoms into the interfacial gate dielectric layer of the core gate all around transistor.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first transistor having a first conductivity type arranged over a substrate. The first transistor includes a first gate electrode layer having a first work function and extending from a first source/drain region to a second source/drain region, and a first channel structure embedded in the first gate electrode layer and extending from the first source/drain region to the second source/drain region. A second transistor having the first conductivity type is arranged laterally beside the first transistor. The second transistor includes a second gate electrode layer having a second work function that is different than the first work function and extending from a third source/drain region to a fourth source/drain region. A second channel structure is embedded in the second gate electrode layer and extends from the third source/drain region to the fourth source/drain region.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.

Abstract: A method of manufacturing a panel assembly includes supporting the panel assembly in a free state using a holding fixture. The panel assembly has a skin panel, and sacrificial material coupled to a skin panel inner surface. The method includes acquiring a free state outer surface contour of the panel assembly by scanning a skin panel outer surface while the panel assembly is supported by the holding fixture. The method also includes developing a numerically controlled (NC) machining program having cutter paths configured for machining the interface locations to an inner surface contour that reflects nominal thicknesses of the panel assembly based off of the free state outer surface contour. In addition, the method includes machining the sacrificial material at the interface locations by moving a cutter along the cutter paths while the panel assembly is supported by the holding fixture.

Abstract: An antenna system with switchable radiation gain includes a signal feeding element, a first antenna element, a second antenna element, a first diode, a first switch element, a second switch element, a first impedance transformer, and a second impedance transformer. The first antenna element is coupled to a first connection point. The second antenna element is coupled to a second connection point. The first diode has an anode coupled to the first connection point, and a cathode coupled to the second connection point. The first switch element and the second switch element are configured to select either the first impedance transformer or the second impedance transformer as a first target transformer, and the selected first target transformer is coupled between the first connection point and the signal feeding element.

Abstract: Some embodiment structures and methods are described. A structure includes an integrated circuit die at least laterally encapsulated by an encapsulant, and a redistribution structure on the integrated circuit die and encapsulant. The redistribution structure is electrically coupled to the integrated circuit die. The redistribution structure includes a first dielectric layer on at least the encapsulant, a metallization pattern on the first dielectric layer, a metal oxide layered structure on the metallization pattern, and a second dielectric layer on the first dielectric layer and the metallization pattern. The metal oxide layered structure includes a metal oxide layer having a ratio of metal atoms to oxygen atoms that is substantially 1:1, and a thickness of the metal oxide layered structure is at least 50 ?. The second dielectric layer is a photo-sensitive material. The metal oxide layered structure is disposed between the metallization pattern and the second dielectric layer.

Abstract: A chip package structure is provided. The chip package structure includes a first substrate. The chip package structure includes a conductive via structure passing through the first substrate. The chip package structure includes a barrier layer over a surface of the first substrate. The chip package structure includes an insulating layer over the barrier layer. The chip package structure includes a conductive pad over the insulating layer and having a first portion and a second portion. The chip package structure includes a conductive bump over the second portion of the conductive pad. A third portion of the conductive pad is between the conductive bump and the conductive via structure from a top view of the conductive pad, the conductive bump, and the conductive via structure.

Abstract: The present disclosure provides a method for a display driver system and a display driver system.

Abstract: A semiconductor device includes a first channel region disposed in a first device region over a substrate; a first gate dielectric layer disposed over the first channel region; a second gate dielectric layer disposed over the second channel region; and a gate electrode disposed over the first gate dielectric layer. The first gate dielectric layer includes a first dipole dopant and the second gate dielectric layer includes a second dipole dopant embedded therein. A boundary between the first gate dielectric layer and the second gat dielectric layer contains the first dipole dopant and the second dipole dopant.

Abstract: An intelligent auxiliary gout diagnosis and treatment system for combination of traditional Chinese medicine and western medicine includes a knowledge extraction module, a predictive reasoning module, an evaluation feedback module and a data storage module. The knowledge extraction module is configured to construct a gout knowledge graph. The predictive reasoning module is configured to learn a predictive model in combination with historical annotation data to perform reasoning diagnosis, predict a gout course stage of a patient and recommend a treatment plan. The evaluation feedback module is configured to evaluate a diagnosis and treatment effect for strengthening the system and improving an intelligent level of the system. The data storage module is configured to store data of the system.

Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive bump over and electrically connected to the chip. The chip package structure includes a ring-like structure over and electrically insulated from the chip. The ring-like structure surrounds the conductive bump, and the ring-like structure and the conductive bump are made of a same material.

Abstract: The present disclosure discloses an optical imaging lens assembly including, sequentially from an object side to an image side along an optical axis, a first lens, a second lens, a third lens, a fourth lens, a fifth lens, and a sixth lens. The first lens has a positive refractive power, both of an object-side surface and an image-side surface thereof are convex surfaces; the second lens has a negative refractive power; the third lens has a negative refractive power, and an image-side surface thereof is a concave surface; the fourth lens has a refractive power; the fifth lens has a refractive power, and an image-side surface thereof is a convex surface; the sixth lens has a refractive power, and an object-side surface thereof is a concave surface. Half of a maximal field-of-view HFOV of the optical imaging lens assembly satisfies HFOV<30°.

Abstract: A semiconductor having a first gate-all-around (GAA) transistor, a second GAA transistor, and a third GAA transistor is provided. The first (GAA) transistor includes a first plurality of channel members, a gate dielectric layer over the first plurality of channel members, a first work function layer over the gate dielectric layer, and a glue layer over the first work function layer. The second GAA transistor include a second plurality of channel members, the gate dielectric layer over the second plurality of channel members, and a second work function layer over the gate dielectric layer, the first work function layer over and in contact with the second work function layer, and the glue layer over the first work function layer. The third GAA transistor includes a third plurality of channel members, the gate dielectric layer over the third plurality of channel members, and the glue layer over the gate dielectric layer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor layers and second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers are separated and stacked up, and a thickness of each second semiconductor layer is less than a thickness of each first semiconductor layer; a first interfacial layer around each first semiconductor layer; a second interfacial layer around each second semiconductor layer; a first dipole gate dielectric layer around each first semiconductor layer and over the first interfacial layer; a second dipole gate dielectric layer around each second semiconductor layer and over the second interfacial layer; a first gate electrode around each first semiconductor layer and over the first dipole gate dielectric layer; and a second gate electrode around each second semiconductor layer and over the second dipole gate dielectric layer.

Abstract: A memory device includes a substrate, a spin-orbit torque (SOT) layer, a magnetic tunneling junction (MTJ) film stack, a connecting via and a shielding structure. The SOT layer is disposed on the substrate. The MTJ film stack is formed over SOT layer and on the substrate. The connecting via is disposed on and electrically connected to the MTJ film stack. The shielding structure is laterally surrounding the MTJ film stack and disposed on the SOT layer, wherein the shielding structure includes a first dielectric layer, a high magnetic permeability layer and a second dielectric layer, the first dielectric layer is in contact with the SOT layer and the MTJ film stack, and the high magnetic permeability layer is sandwiched between the first dielectric layer and the second dielectric layer.