Patents by Inventor Lin Tsai

Lin Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240387719
    Abstract: Various embodiments of the present disclosure are directed toward an integrated chip including an undoped layer overlying a substrate. A first barrier layer overlies the undoped layer. A doped layer overlies the first barrier layer. Further, a second barrier layer overlies the first barrier layer, where the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance. The first and second barrier layers comprise a same III-V semiconductor material. A first atomic percentage of a first element within the first barrier layer is less than a second atomic percentage of the first element within the second barrier layer.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 21, 2024
    Inventors: Yun-Hsiang Wang, Chun Lin Tsai, Jiun-Lei Jerry Yu, Po-Chih Chen, Chia-Ling Yeh, Ching Yu Chen
  • Patent number: 12148144
    Abstract: A wafer inspection system is provided. The wafer inspection system includes a memory unit configured to store an image of a device under test (DUT) on a wafer, an image-uploading unit configured to upload the image to a processing unit, and a processing unit. The processing unit is configured to identify a plurality of candidate regions on the image; generate a confidence score for each of the plurality of candidate regions, wherein the confidence score indicates a probability of a candidate region including a probe mark; select a first candidate region having the highest confidence score as a selected region; determine whether a second candidate region in the plurality of candidate regions includes the same probe mark as the first candidate region; and eliminate the second candidate region if the second candidate region includes the same probe mark as the first candidate region.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: November 19, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chia-Lin Tsai, Hung-Ru Li, Wun-Ye Ku
  • Publication number: 20240379836
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a gallium nitride (GaN) layer on a substrate; an aluminum gallium nitride (AlGaN) layer disposed on the GaN layer; a gate stack disposed on the AlGaN layer; a source feature and a drain feature disposed on the AlGaN layer and interposed by the gate stack; a dielectric material layer is disposed on the gate stack; and a field plate disposed on the dielectric material layer and electrically connected to the source feature, wherein the field plate includes a step-wise structure.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Wei Wang, Wei-Chen Yang, Yao-Chung Chang, Ru-Yi Su, Yen-Ku Lin, Chuan-Wei Tsou, Chun Lin Tsai
  • Patent number: 12140863
    Abstract: An imprint method includes the following steps. A first resist layer is formed on a first substrate. A first imprinting step using a first mold is performed to the first resist layer. A first etching process is performed to the first substrate with the first resist layer as an etching mask after the first imprinting step so as to form a first recess pattern in the first substrate. A second resist layer is formed on the first substrate. A second imprinting step using a second mold is performed to the second resist layer. A second etching process is performed to the first substrate with the second resist layer as an etching mask after the second imprinting step so as to form second recess patterns in the first substrate. A depth of the first recess pattern is greater than a depth of each of the second recess patterns.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: November 12, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Su-Yun Fang, Chih-Hsien Tang, Yi-Lin Tsai
  • Publication number: 20240371951
    Abstract: Various embodiments of the present disclosure are directed towards a two-dimensional carrier gas (2DCG) semiconductor device comprising an ohmic source/drain electrode with a plurality of protrusions separated by gaps and protruding from a bottom surface of the ohmic source/drain electrode. The ohmic source/drain electrode overlies a semiconductor film, and the protrusions extend from the bottom surface into the semiconductor film. Further, the ohmic source/drain electrode is separated from another ohmic source/drain electrode that also overlies the semiconductor film. The semiconductor film comprises a channel layer and a barrier layer that are vertically stacked and directly contact at a heterojunction. The channel layer accommodates a 2DCG that extends along the heterojunction and is ohmically coupled to the ohmic source/drain electrode and the other ohmic source/drain electrode. A gate electrode overlies the semiconductor film between the ohmic source/drain electrode and the other source/drain electrode.
    Type: Application
    Filed: July 18, 2024
    Publication date: November 7, 2024
    Inventors: Shih-Chien Liu, Yao-Chung Chang, Chun Lin Tsai
  • Publication number: 20240371954
    Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate, an active region on the substrate, and a first transistor having a gate structure, a source conductor, and a drain conductor disposed on the active region, wherein the drain conductor and the source conductor are disposed on opposite sides of the gate structure, and the source conductor is shorter than the drain conductor.
    Type: Application
    Filed: May 7, 2023
    Publication date: November 7, 2024
    Inventors: WAN-LIN TSAI, CLEMENT HSINGJEN WANN, YI-JING LI, I-SHENG CHEN, SHIH-CHUN FU, KAI-QIANG WEN
  • Patent number: 12136597
    Abstract: A semiconductor package includes a first die structure, a first redistribution structure that is disposed on the first die structure, a second die structure that is disposed on the first redistribution structure, and a second redistribution structure that is disposed on the second die structure. The first die structure includes an interposer, and the interposer includes a semiconductor substrate and through-vias that penetrate through the semiconductor substrate. A first integrated circuit die is disposed in the semiconductor substrate of the interposer. The second die structure includes a second integrated circuit die that is encapsulated in an encapsulant and several conductive pillars that penetrate through the encapsulant. The first integrated circuit die is electrically connected to the second integrated circuit die through the first redistribution structure, the conductive pillars, and the second redistribution structure.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: November 5, 2024
    Assignee: MEDIATEK INC.
    Inventors: Yi-Lin Tsai, Nai-Wei Liu, Wen-Sung Hsu
  • Patent number: 12132088
    Abstract: Various embodiments of the present disclosure are directed towards a two-dimensional carrier gas (2DCG) semiconductor device comprising an ohmic source/drain electrode with a plurality of protrusions separated by gaps and protruding from a bottom surface of the ohmic source/drain electrode. The ohmic source/drain electrode overlies a semiconductor film, and the protrusions extend from the bottom surface into the semiconductor film. Further, the ohmic source/drain electrode is separated from another ohmic source/drain electrode that also overlies the semiconductor film. The semiconductor film comprises a channel layer and a barrier layer that are vertically stacked and directly contact at a heterojunction. The channel layer accommodates a 2DCG that extends along the heterojunction and is ohmically coupled to the ohmic source/drain electrode and the other ohmic source/drain electrode. A gate electrode overlies the semiconductor film between the ohmic source/drain electrode and the other source/drain electrode.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: October 29, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chien Liu, Yao-Chung Chang, Chun Lin Tsai
  • Publication number: 20240355711
    Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) chip comprising a front-end-of-line (FEOL) through semiconductor-on-substrate via (TSV), as well as a method for forming the IC chip. In some embodiments, a semiconductor layer overlies a substrate. The semiconductor layer may, for example, be or comprise a group III-V semiconductor and/or some other suitable semiconductor(s). A semiconductor device is on the semiconductor layer, and a FEOL layer overlies the semiconductor device. The FEOL TSV extends through the FEOL layer and the semiconductor layer to the substrate at a periphery of the IC chip. An intermetal dielectric (IMD) layer overlies the FEOL TSV and the FEOL layer, and an alternating stack of wires and vias is in the IMD layer.
    Type: Application
    Filed: July 2, 2024
    Publication date: October 24, 2024
    Inventors: Yun-Hsiang Wang, Chun Lin Tsai, Jiun-Lei Jerry Yu, Po-Chih Chen
  • Publication number: 20240355761
    Abstract: In some embodiments, the present disclosure relates to a semiconductor structure. The semiconductor substrate includes a semiconductor material over a base substrate. The semiconductor substrate has one or more sidewalls forming a crack stop trench that is laterally between a central region of the semiconductor substrate and a peripheral region of the semiconductor substrate that surrounds the central region. The peripheral region of the semiconductor substrate includes a plurality of cracks.
    Type: Application
    Filed: July 1, 2024
    Publication date: October 24, 2024
    Inventors: Jiun-Yu Chen, Chun-Lin Tsai, Yun-Hsiang Wang, Chia-Hsun Wu, Jiun-Lei Yu, Po-Chih Chen
  • Patent number: 12115550
    Abstract: A dual-valve automatic calibration system comprises a primary positioner, a first secondary positioner and a second secondary positioner: the first secondary positioner and the second secondary positioner are connected with a first fluid coating unit and a second fluid coating unit, respectively; the primary positioner comprises a primary X-axis positioner and a primary Y-axis positioner; both the first secondary positioner and the second secondary positioner are connected with the primary X-axis positioner. In contrast to the prior art that a secondary positioner is installed on a primary Z-axis positioner, a dual-valve automatic calibration system contributes to promotion of positioning precision on the Z-axis and reduction of a burden imposed on the Z-axis.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: October 15, 2024
    Assignee: Kulicke and Soffa Hi-Tech Co., Ltd.
    Inventors: Lu-Min Chen, Tsung-Lin Tsai
  • Publication number: 20240332411
    Abstract: In some embodiments, the present disclosure relates to a semiconductor device. The semiconductor device includes a channel layer over a base substrate and an active layer over the channel layer. A source and a drain are over the active layer. A gate is over the active layer and laterally between the source and the drain. A dielectric is over the active layer and laterally surrounds the source, the drain, and the gate. A cap structure laterally contacts the source and is disposed laterally between the gate and the source. The source vertically extends to a top of the cap structure.
    Type: Application
    Filed: June 11, 2024
    Publication date: October 3, 2024
    Inventors: Ming-Cheng Lin, Chen-Bau Wu, Chun Lin Tsai, Haw-Yun Wu, Liang-Yu Su, Yun-Hsiang Wang
  • Patent number: 12107156
    Abstract: A semiconductor structure includes: a channel layer; an active layer over the channel layer, wherein the active layer is configured to form a two-dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer; a gate electrode over a top surface of the active layer; and a source/drain electrode over the top surface of the active layer; wherein the active layer includes a first layer and a second layer sequentially disposed therein from the top surface to a bottom surface of the active layer, and the first layer possesses a higher aluminum (Al) atom concentration compared to the second layer. An HEMT structure and an associated method are also disclosed.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: October 1, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yao-Chung Chang, Po-Chih Chen, Jiun-Lei Jerry Yu, Chun Lin Tsai
  • Publication number: 20240321736
    Abstract: The present disclosure relates an integrated chip. The integrated chip includes an isolation region disposed within a substrate and surrounding an active area. A gate structure is disposed over the substrate and has a base region and a gate extension finger protruding outward from a sidewall of the base region along a first direction to past opposing sides of the active area. A source contact and a drain contact are disposed within the active area. The drain contact is separated from the source contact by the gate extension finger. A first plurality of conductive contacts are arranged on the gate structure. The first plurality of conductive contacts are separated along the first direction by distances overlying the gate extension finger.
    Type: Application
    Filed: June 3, 2024
    Publication date: September 26, 2024
    Inventors: Shih-Pang Chang, Haw-Yun Wu, Yao-Chung Chang, Chun-Lin Tsai
  • Publication number: 20240315877
    Abstract: An eyeshade structure for bilirubin detection includes a body, a first detection module, and a second detection module. The body includes a bottom plate and a side wall. The side wall is connected to the bottom plate and forms an accommodating space with the bottom plate. The first detection module is arranged on the bottom plate. The second detection module is arranged on the bottom plate and is adjacent to the first detection module. The first detection module and the second detection module each include a circuit board, a light-emitting element, an inner photographing element, and an outer photographing element. The circuit board is connected to the bottom plate. The light-emitting element is electrically connected to the circuit board. The inner photographing element is electrically connected to the circuit board. The outer photographing element is electrically connected to the circuit board.
    Type: Application
    Filed: September 18, 2023
    Publication date: September 26, 2024
    Applicant: PolyVisions Technology Co., Ltd.
    Inventors: Chih-Ju Lin, Yi-Wei Liu, Lee-Lin Tsai
  • Patent number: 12100757
    Abstract: In some embodiments, the present disclosure relates to a method of forming a high electron mobility transistor (HEMT) device. The method includes forming a passivation layer over a substrate. A source contact and a drain contact are formed within the passivation layer. A part of the passivation layer is removed to form a cavity. The cavity has a lower portion formed by a first sidewall and a second sidewall of the passivation layer and an upper portion formed by the first sidewall of the passivation layer and a sidewall of the source contact. A gate structure is formed within the passivation layer between the drain contact and the cavity. A cap structure is formed within the cavity.
    Type: Grant
    Filed: July 7, 2023
    Date of Patent: September 24, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Cheng Lin, Chen-Bau Wu, Chun Lin Tsai, Haw-Yun Wu, Liang-Yu Su, Yun-Hsiang Wang
  • Publication number: 20240312889
    Abstract: An electronic package and a circuit structure thereof are provided, in which a circuit layer and an electrical function part are formed on a dielectric layer of the circuit structure, and the dielectric layer has at least one corner at a right angle, where a shape of the electrical function part at the corner and corresponding to the right angle is of a non-right angle shape and/or a routing path of the circuit layer at the corner and corresponding to the right angle is of a non-right angle shape, so that stress concentration can be reduced, thereby preventing the electronic package from warping.
    Type: Application
    Filed: June 30, 2023
    Publication date: September 19, 2024
    Inventors: Fang-Lin TSAI, Wei-Son TSAI, Kun-Yuan LUO, Pei-Geng WENG, Ching-Hung TSENG
  • Patent number: 12094838
    Abstract: In some embodiments, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a stacked semiconductor substrate having a semiconductor material disposed over a base semiconductor substrate. The base semiconductor substrate has a first coefficient of thermal expansion and the semiconductor material has a second coefficient of thermal expansion that is different than the first coefficient of thermal expansion. The stacked semiconductor substrate includes one or more sidewalls defining a crack stop ring trench that continuously extends in a closed path between a central region of the stacked semiconductor substrate and a peripheral region of the stacked semiconductor substrate surrounding the central region. The peripheral region of the stacked semiconductor substrate includes a plurality of cracks and the central region is substantially devoid of cracks.
    Type: Grant
    Filed: July 20, 2023
    Date of Patent: September 17, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Yu Chen, Chun-Lin Tsai, Yun-Hsiang Wang, Chia-Hsun Wu, Jiun-Lei Yu, Po-Chih Chen
  • Patent number: 12087820
    Abstract: A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.
    Type: Grant
    Filed: April 17, 2023
    Date of Patent: September 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Syuan Lin, Jiun-Lei Yu, Ming-Cheng Lin, Chun Lin Tsai
  • Publication number: 20240297120
    Abstract: A semiconductor package structure includes a first redistribution layer, a first semiconductor die, a second semiconductor die, a bridge structure, and a plurality of conductive bumps. The first semiconductor die and the second semiconductor die are disposed over the first redistribution layer. The bridge structure is disposed under the first redistribution layer. The first semiconductor die is electrically coupled to the second semiconductor die through the first redistribution layer and the bridge structure. The conductive bumps are disposed under the first redistribution layer and are coupled to the first redistribution layer. The bridge structure is disposed between at least two of the conductive bumps.
    Type: Application
    Filed: January 9, 2024
    Publication date: September 5, 2024
    Inventors: Wei-Yu CHEN, Yi-Lin TSAI, Nai-Wei LIU, Shih-Chin LIN, Wen-Sung HSU