Abstract: The transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer.

Abstract: A dual-valve automatic calibration system comprises a primary positioner, a first secondary positioner and a second secondary positioner: the first secondary positioner and the second secondary positioner are connected with a first fluid coating unit and a second fluid coating unit, respectively; the primary positioner comprises a primary X-axis positioner and a primary Y-axis positioner; both the first secondary positioner and the second secondary positioner are connected with the primary X-axis positioner. In contrast to the prior art that a secondary positioner is installed on a primary Z-axis positioner, a dual-valve automatic calibration system contributes to promotion of positioning precision on the Z-axis and reduction of a burden imposed on the Z-axis.

Abstract: In some embodiments, the present disclosure relates to a method of forming a high electron mobility transistor (HEMT) device. The method includes forming a passivation layer over a substrate. A source contact and a drain contact are formed within the passivation layer. A part of the passivation layer is removed to form a cavity. The cavity has a lower portion formed by a first sidewall and a second sidewall of the passivation layer and an upper portion formed by the first sidewall of the passivation layer and a sidewall of the source contact. A gate structure is formed within the passivation layer between the drain contact and the cavity. A cap structure is formed within the cavity.

Abstract: A jetting valve with two stage calibrating structures is disclosed, the jetting valve includes: a casing having an accommodating space; a piezoelectric actuating unit disposed on one side of the accommodating space; a spraying unit disposed on the other side of the accommodating space; a displacement amplifying element is arranged at the bottom of the accommodating space and leans against on the spraying unit, the bottom end of the piezoelectric driving unit is in contact with the displacement amplifying element; a sensing unit is arranged on the periphery of the displacement amplifying element to sense the movement of the spraying unit; a control unit, connected to the sensing unit and the piezoelectric actuating unit, adjusting the voltage supplied to the piezoelectric driving unit according to data obtained by the sensing unit; and a liquid supply unit connected to the spraying unit.

Abstract: A glue dispensing device comprises a base, a pressure control unit, a quantitative glue supply unit and a glue dispensing needle. The base comprises a pressure control chamber and a glue tube body, the pressure control chamber is located inside the base, the glue tube body extends from one end of the base to the other end, and the glue tube body penetrates the pressure control chamber. The pressure control unit is coupled to the pressure control chamber. The quantitative glue supply unit is disposed at one end of the base body and is coupled to the glue tube body. The glue dispensing needle is disposed at the other end of the base and is coupled to the glue tube body. The glue dispensing device uses the pressure change of the pressure control chamber to deform the glue tube body, thereby achieving quantitative glue dispensing effect with accuracy and stability. In addition, a glue dispensing method is also disclosed.

Abstract: An imprint method includes the following steps. A first resist layer is formed on a first substrate. A first imprinting step using a first mold is performed to the first resist layer. A first etching process is performed to the first substrate with the first resist layer as an etching mask after the first imprinting step so as to form a first recess pattern in the first substrate. A second resist layer is formed on the first substrate. A second imprinting step using a second mold is performed to the second resist layer. A second etching process is performed to the first substrate with the second resist layer as an etching mask after the second imprinting step so as to form second recess patterns in the first substrate. A depth of the first recess pattern is greater than a depth of each of the second recess patterns.

Abstract: A reciprocating glue dispenser dispensing switch includes a switching device main body, a needle holding base, a sliding wear-resistant plate, and a driving device. The switching device main body is equipped with a double liquid inlet, the needle holding base is equipped with a mixed glue outlet, the sliding wear-resistant plate is installed between the switching device main body and the needle holding base, and the sliding wear-resistant plate is equipped with a sliding wear-resistant plate opening. The driving device is utilized to move the sliding wear-resistant plate. A mixed double-liquid glue passes through the double liquid inlet, the sliding wear-resistant plate opening and the glue outlet to dispense a mixed double-liquid glue while the double liquid inlet, the sliding wear-resistant plate opening and the glue outlet are overlapped.

Abstract: A method of forming a high electron mobility transistor (HEMT) includes a first III-V compound layer and a second III-V compound layer disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are disposed on the second III-V compound layer. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A capping layer is disposed on the second III-V compound layer.

Abstract: An electronic package is provided and includes a substrate structure, an electronic element disposed on the substrate structure and an encapsulation layer encapsulating the electronic element, where at least one functional circuit is formed on a surface of a substrate body of the substrate structure, and a wire having a smaller width is arranged on a boundary line at a junction between an encapsulation area and a peripheral area, so that when a mold for forming the encapsulation layer is formed to cover the substrate structure, the mold will create a gap around the wire to serve as an exhaust passage. Therefore, when the encapsulation layer is formed, the exhaust passage can be used to exhaust air, so as to avoid problems such as the occurrence of voids or overflows of the encapsulation layer.

Abstract: A semiconductor device includes a first semiconductor structure including a first high electron mobility transistor (HEMT) device, wherein the first HEMT device includes a first gate, a first source, and a first drain; and a second semiconductor structure stacked above and bonded to the first semiconductor structure, wherein the second semiconductor structure includes a second HEMT device and a third HEMT device, wherein the second HEMT device includes a second gate, a second source, and a second drain that is electrically connected to the first source, wherein the third HEMT device includes a third gate, a third source, and a third drain that is electrically connected to the first gate.

Abstract: In some embodiments, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a stacked semiconductor substrate having a semiconductor material disposed over a base semiconductor substrate. The base semiconductor substrate has a first coefficient of thermal expansion and the semiconductor material has a second coefficient of thermal expansion that is different than the first coefficient of thermal expansion. The stacked semiconductor substrate includes one or more sidewalls defining a crack stop ring trench that continuously extends in a closed path between a central region of the stacked semiconductor substrate and a peripheral region of the stacked semiconductor substrate surrounding the central region. The peripheral region of the stacked semiconductor substrate includes a plurality of cracks and the central region is substantially devoid of cracks.

Abstract: A wafer inspection method is provided. The wafer inspection method includes identifying a plurality of candidate regions on an image of a DUT on a wafer; generating a confidence score for each of the plurality of candidate regions, wherein the confidence score indicates a probability of a candidate region including a probe mark; selecting a first candidate region having the highest confidence score as a selected region; determining whether a second candidate region in the plurality of candidate regions includes the same probe mark as the first candidate region; and eliminating the second candidate region if the second candidate region includes the same probe mark as the first candidate region.

Abstract: A wafer inspection system is provided. The wafer inspection system includes a memory unit configured to store an image of a device under test (DUT) on a wafer, an image-uploading unit configured to upload the image to a processing unit, and a processing unit. The processing unit is configured to identify a plurality of candidate regions on the image; generate a confidence score for each of the plurality of candidate regions, wherein the confidence score indicates a probability of a candidate region including a probe mark; select a first candidate region having the highest confidence score as a selected region; determine whether a second candidate region in the plurality of candidate regions includes the same probe mark as the first candidate region; and eliminate the second candidate region if the second candidate region includes the same probe mark as the first candidate region.

Abstract: In some embodiments, the present disclosure relates to a transistor device. The transistor device that includes a source contact disposed over a substrate. The source contact has a first side and an opposing second side disposed between a first end and an opposing second end. A drain contact is disposed over the substrate and is separated from the source contact along a first direction. A gate structure is disposed over the substrate between the source contact and the drain contact. The gate structure extends along the first side of the source contact facing the drain contact and also wraps around the first end and the opposing second end of the source contact.

Abstract: An electronic package is provided, where a circuit layer and a metal layer having a plurality of openings are formed on a dielectric layer of a circuit portion to reduce the area ratio of the metal layer to the dielectric layer, so as to reduce stress concentration and prevent warping of the electronic package.

Abstract: Various embodiments of the present disclosure are directed towards a three-dimensional (3D) IC comprising semiconductor substrates with different bandgaps. The 3D IC chip comprises a first IC chip and a second IC chip overlying and bonded to the first IC chip. The first IC chip comprises a first semiconductor substrate with a first bandgap, and further comprises and a first device on and partially formed by the first semiconductor substrate. The second IC chip comprises a second semiconductor substrate with a second bandgap different than the first bandgap, and further comprises a second device on the second semiconductor substrate.

Abstract: A display device including a display panel, an image capture element, and a processor is disclosed. The display panel displays a display screen, and to display an on screen display on the display screen. The image capture element captures an image. The processor analyzes the image to obtain an operator location information of an operator of the image and performs a face recognition operation corresponding to the operator, performs an eye recognition operation corresponding to the operator to obtain an operator eye information of the operator, and determines a display position and a display size of the on screen display on the display screen according to the operator location information and the operator eye information. The display panel displays the on screen display on the display screen according to the display position and the display size.

Abstract: A mass transferring system and the method thereof are provided. The system includes two platforms and a plurality of picking and placing units. When the mass transferring process is performed for one of the substrates, the replacing process and the aligning process are simultaneously executed for another one of the substrates, such that the mass transferring process and the replacing process can be performed at the same time. Compared with the conventional mass transferring processes, the efficiency of the mass transferring system and the method thereof according to the present invention can be increased by 90%.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate. A doped isolation region is disposed within the substrate and includes a horizontally extending segment and one or more vertically extending segments extending outward from the horizontally extending segment. The substrate includes a first sidewall and a second sidewall separated from the first sidewall a non-zero distance. The non-zero distance is directly over the one or more vertically extending segments.

Abstract: A packet information analysis method and a network traffic monitoring device are disclosed. The method includes the following. Network flow data including a plurality of network packets is obtained. An index parameter is generated according to packet information (e.g., header information) of the first network packet among the network flow. A target mapping model is determined from a plurality of candidate mapping models according to the index parameter. The index parameter is between a first sampling point and a second sampling point of the target mapping model. An interpolation mapping value is obtained according to the index parameter, the first sampling point, the second sampling point, and the target mapping model. An evaluation value is obtained according to the interpolation mapping value. The evaluation value reflects a distribution status of a monitoring item in the network traffic flows.