Patents by Inventor Lin Wang

Lin Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11987662
    Abstract: An environmentally-friendly flexible conductive polyurethane (PU) and a preparation method thereof are disclosed. The environmentally-friendly flexible conductive PU is prepared by subjecting a mixture of a component A and a component B in a specified mass ratio to in-situ solvent-free polymerization, where the component A is prepared from a polyol, a T-type chain extender, a diselenide diol, high-conductivity carbon black, a dispersing agent, a catalyst, and a leveling agent, and the component B is prepared from a polyisocyanate, a polyol, a multi-walled carbon nanotube (MWCNT), and a dispersing agent. The PU has a reliable electrically-conductive function, and shows a self-healing function under room temperature or light conditions when damaged, wherein a microphase separation value HBI (0.5 to 3.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: May 21, 2024
    Assignees: SHAOXING-KEQIAO INSTISUTE OF ZHEJIANG SCI-TECH UNIVERSITY CO., LTD., ZHEJIANG SCI-TECH UNIVERSITY
    Inventors: Dongming Qi, Zhichao Huang, Qianjun Tian, Lin Wang, Chenghai Liu
  • Patent number: 11980785
    Abstract: A foam production method includes mixing liquid nitrogen with a foaming material to produce foam. A gas is produced in situ from liquid nitrogen. As the ratio of the volume of the gas produced by gasification of liquid nitrogen to the volume of the liquid nitrogen is relatively high, when a large gas supply flow is needed to generate a large foam flow, a liquid nitrogen storage device of a small volume can be used instead of bulky air supply devices such as high-pressure gas cylinders, air compressors, air compressor sets and the like, reducing the volume of the air supply device. In addition, the liquid nitrogen used in foaming will release nitrogen gas after the foam blast, such that the nitrogen is also able to inhibit combustion on the surface of burning materials, accelerating the extinguishing of the fire.
    Type: Grant
    Filed: January 19, 2023
    Date of Patent: May 14, 2024
    Assignees: CHINA PETROLEUM & CHEMICAL CORPORATION, CHINA PETROLEUM & CHEMICAL CORPORATION QINGDAO RESEARCH INSTITUTE OF SAFETY ENGINEERING
    Inventors: Shanjun Mu, Chunming Jiang, Weihua Zhang, Quanzhen Liu, Xuqing Lang, Xiaodong Mu, Lin Wang, Jingfeng Wu, Longmei Tan, Zuzheng Shang, Rifeng Zhou, Jianxiang Li, Hui Yu
  • Publication number: 20240155175
    Abstract: This application provides techniques of generating interactive videos. The techniques comprise obtaining an original video, creating an interactive track for the original video to obtain an initial video, and adding an interactive component to the interactive track; and generating an interactive video by rendering at least one interactive video frame and other video frames of the initial video based on the interactive component. In this way, an interactive video with an interactive capability can be generated without additionally adding a data channel to implement an interaction function, thereby reducing processing load of a terminal and reducing resource consumption of the terminal.
    Type: Application
    Filed: January 20, 2022
    Publication date: May 9, 2024
    Inventors: Chaoran LI, Hao WANG, Zhicong ZANG, Zhong DONG, Zhaozheng WANG, Yicong MEI, Lin WANG
  • Patent number: 11979479
    Abstract: A packet sorting and reassembly circuit module, including a header parser, an information processing circuit, at least one state tracking and reassembly circuit, and an output arbiter, is provided. The header parser is configured to analyze multiple first packet segments to obtain header information corresponding to a first network packet, wherein the first network packet is transmitted based on a transmission control protocol (TCP) communication protocol. The information processing circuit is configured to transmit the first packet segments and sideband information corresponding to the first packet segments to a first state tracking and reassembly circuit among the at least one state tracking and reassembly circuit according to the header information. The first state tracking and reassembly circuit is configured to reassemble and sort the first packet segments according to the sideband information. The output arbiter is configured to output the first packet segments according to a sorting result.
    Type: Grant
    Filed: January 16, 2023
    Date of Patent: May 7, 2024
    Assignees: Chung Yuan Christian University, KGI Securities Co. Ltd.
    Inventors: Yu-Kuen Lai, Chao-Lin Wang, He-Ping Li, Cheng-Han Chuang, Kai-Po Chang
  • Publication number: 20240145903
    Abstract: Base station antennas are provided. A base station antenna includes a reflector that has a plurality of faces that face in different directions. The base station antenna includes a plurality of arrays of radiating elements that are on the faces, respectively, of the reflector. Moreover, the base station antenna includes a plurality of parasitic elements that are on the faces. Related methods of operating a base station antenna are also provided.
    Type: Application
    Filed: June 28, 2023
    Publication date: May 2, 2024
    Inventors: Lin Wang, Jianpeng Lu, Haiyan Chen, Hangsheng Wen
  • Publication number: 20240142175
    Abstract: Disclosed are an unblocking apparatus for a furnace discharging pipe and a use method. The unblocking apparatus includes a rail, a rail car that may move along the rail, an unblocking drive mechanism arranged on the rail car, a heat-unblocking component, a cold-unblocking component, and a material receiving component that is used to receive a blocking material in the discharging pipe, and a drive end of the unblocking drive mechanism is detachably connected with one end of the heat-unblocking component and the cold-unblocking component respectively. The present application effectively handles different blockage situations of the furnace discharging pipe by connecting the unblocking drive mechanism with an unblocking rod capable of heat-unblocking and a drilling rod capable of cold-unblocking, thereby two modes of heat-unblocking and cold-unblocking are performed on the furnace discharging pipe; and the discharging pipe may be unblocked by a remote operation.
    Type: Application
    Filed: October 23, 2023
    Publication date: May 2, 2024
    Applicants: China Nuclear Sichuan Environmental Protection Engineering Co., Ltd., China Building Materials Academy, China Nuclear Power Engineering Co., Ltd.
    Inventors: Weidong XU, Yu CHANG, Yongchang ZHU, Hong DUAN, Chunyu TIAN, Wei WU, Debo YANG, Qingbin ZHAO, Shuaizhen WU, Lin WANG, Zhu CUI, Heyi GUO, Maosong FAN, Yuancheng SUN, Jie MEI, Xiaoli AN, Yongxiang ZHAO, Qinda LIU
  • Publication number: 20240137431
    Abstract: A packet sorting and reassembly circuit module, including a header parser, an information processing circuit, at least one state tracking and reassembly circuit, and an output arbiter, is provided. The header parser is configured to analyze multiple first packet segments to obtain header information corresponding to a first network packet, wherein the first network packet is transmitted based on a transmission control protocol (TCP) communication protocol. The information processing circuit is configured to transmit the first packet segments and sideband information corresponding to the first packet segments to a first state tracking and reassembly circuit among the at least one state tracking and reassembly circuit according to the header information. The first state tracking and reassembly circuit is configured to reassemble and sort the first packet segments according to the sideband information. The output arbiter is configured to output the first packet segments according to a sorting result.
    Type: Application
    Filed: January 16, 2023
    Publication date: April 25, 2024
    Applicants: Chung Yuan Christian University, KGI Securities Co. Ltd.
    Inventors: Yu-Kuen Lai, Chao-Lin Wang, He-Ping Li, Cheng-Han Chuang, Kai-Po Chang
  • Publication number: 20240135497
    Abstract: Embodiments of the present application provide an image enhancement method, a chip, and an image acquisition device. The method comprises: storing, by a main processor, a preset number of Raw image frames to be processed currently acquired from a sensor in a first off-chip memory, into the on-chip memory; performing, by a first neural network processor, image fusion on a preset number of Raw image frames to be fused currently obtained based on the preset number of Raw image frames to be processed currently in the on-chip memory based on a preset image fusion network, to obtain a fused Raw image frame, and storing it into the on-chip memory; sending, by the main processor to an ISP chip, a target Raw image frame to be sent currently obtained based on the fused Raw image frame in the on-chip memory.
    Type: Application
    Filed: August 29, 2023
    Publication date: April 25, 2024
    Inventors: Zaichu YANG, Caizhi ZHU, Shengning XIANG, Lin WANG
  • Publication number: 20240127535
    Abstract: A method includes: obtaining and splicing a plurality of frames of point cloud data to obtain a complete point cloud model of an indoor structure; extracting point cloud plane features corresponding to the complete point cloud model, and classifying the point cloud plane features into indoor structure types comprising a floor, a wall, and a ceiling; projecting point cloud data of the wall onto a plane of the floor to generate a planar grid graph; and generating a two-dimensional plane view of the indoor structure based on the planar grid graph.
    Type: Application
    Filed: December 26, 2023
    Publication date: April 18, 2024
    Inventors: YueYu LIN, Haoli Zhou, Lin Wang
  • Publication number: 20240130246
    Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.
    Type: Application
    Filed: December 25, 2023
    Publication date: April 18, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Ju-Chun Fan, Ching-Hua Hsu, Yi-Yu Lin, Hung-Yueh Chen
  • Patent number: 11960199
    Abstract: A projection screen includes an optical collimating layer and a surface diffusion layer which are arranged in sequence. A grating absorption layer for absorbing ambient light from various directions except a projection light direction is also provided between the optical collimating layer and the surface diffusion layer. The grating absorption layer includes a plurality of light-absorption ring-shaped units with different radii. The plurality of light-absorption ring-shaped units are arranged in a concentric ring. Each of the light-absorption ring-shaped units consists of a plurality of gratings arranged in the circumferential direction of the concentric ring. By taking a vertical symmetrical center line of the projection screen as a center, in a direction extending along the circumferential direction of the concentric ring to the left side and the right side of the projection screen, the distance between two adjacent gratings in the same light-absorption ring-shaped unit gradually increases.
    Type: Grant
    Filed: June 28, 2020
    Date of Patent: April 16, 2024
    Assignee: APPOTRONICS CORPORATION LIMITED
    Inventors: Fei Hu, Wei Sun, Lin Wang, Yi Li
  • Patent number: 11962296
    Abstract: Disclosed herein is a flexible sensing interface, comprising: a sensor, comprising: a core; an inner electrode in the form of a conductive material in contact with the core; an inner dielectric material substantially encasing the inner electrode; an outer electrode in the form of a conductive material in contact with the inner dielectric material and in electrical communication with the inner electrode; and an outer dielectric material substantially encasing the outer electrode; wherein the inner dielectric material and the outer dielectric material comprise an elastic material. Also disclosed herein are systems and methods for making and using the same.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: April 16, 2024
    Assignee: Georgia Tech Research Corporation
    Inventors: Seyedeh Fereshteh Shahmiri, Chaoyu Chen, Gregory D. Abowd, Shivan Mittal, Thad Eugene Starner, Yi-Cheng Wang, Zhong Lin Wang, Dingtian Zhang, Steven L. Zhang, Anandghan Waghmare
  • Patent number: 11963460
    Abstract: A method for manufacturing a memory device is provided. The method includes etching an opening in a first dielectric layer; forming a bottom electrode, a resistance switching element, and a top electrode in the opening in the first dielectric layer; forming a second dielectric layer over the bottom electrode, the resistance switching element, and the top electrode; and forming an electrode via connected to a top surface of the top electrode in the second dielectric layer.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Hsiang Tseng, Chih-Lin Wang, Yi-Huang Wu
  • Patent number: 11957061
    Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts top surfaces of the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Ju-Chun Fan, Yi-Yu Lin, Ching-Hua Hsu, Hung-Yueh Chen
  • Patent number: 11956972
    Abstract: A semiconductor memory device includes a substrate having a memory area and a logic circuit area thereon, a first interlayer dielectric layer on the substrate, and a second interlayer dielectric layer on the substrate. An embedded memory cell structure is disposed within the memory area between the first interlayer dielectric layer and the second interlayer dielectric layer. The second interlayer dielectric layer includes a first portion covering the embedded memory cell structure within the memory area and a second portion covering the logic circuit area. A top surface of the first portion is coplanar with a top surface of the second portion.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Si-Han Tsai, Ching-Hua Hsu, Chen-Yi Weng, Po-Kai Hsu
  • Patent number: 11957064
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.
    Type: Grant
    Filed: October 18, 2022
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • Publication number: 20240111588
    Abstract: Intelligent process management is provided. A start time is determined for an additional process to be run on a worker node within a duration of a sleep state of a task of a process already running on the worker node by adding a first defined buffer time to a determined start time of the sleep state of the task. A backfill time is determined for the additional process by subtracting a second defined buffer time from a determined end time of the sleep state of the task. A scheduling plan is generated for the additional process based on the start time and the backfill time corresponding to the additional process. The scheduling plan is executed to run the additional process on the worker node according to the start time and the backfill time corresponding to the additional process.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Inventors: Jing Jing Wei, Yue Wang, Shu Jun Tang, Yang Kang, Yi Fan Wu, Qi Han Zheng, Jia Lin Wang
  • Publication number: 20240114803
    Abstract: A method for fabricating semiconductor device includes the step of forming a magnetic tunneling junction (MTJ) on a substrate, in which the MTJ includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer and the free layer includes a magnesium oxide (MgO) compound. According to an embodiment of the present invention, the free layer includes a first cap layer on the barrier layer, a spacer on the first cap layer, and a second cap layer on the spacer.
    Type: Application
    Filed: October 24, 2022
    Publication date: April 4, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventor: Hui-Lin Wang
  • Patent number: 11950431
    Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.
    Type: Grant
    Filed: December 2, 2022
    Date of Patent: April 2, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei Chen, Hui-Lin Wang, Yu-Ru Yang, Chin-Fu Lin, Yi-Syun Chou, Chun-Yao Yang
  • Patent number: 11950513
    Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: April 2, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Wei Chen, Po-Kai Hsu, Yu-Ping Wang, Hung-Yueh Chen