Patents by Inventor Lin Wei
Lin Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250138237Abstract: A light emitting module includes a transparent substrate, a plurality of first light emitting components, a light guide plate and a plurality of second light emitting components. The transparent substrate includes a first surface and a second surface that are opposite to each other. The plurality of first light emitting components are arranged in an array on the first surface. The light guide plate is disposed on the second surface. The plurality of second light emitting components are disposed on the second surface and face the light incident side surface of the light guide plate.Type: ApplicationFiled: September 30, 2024Publication date: May 1, 2025Applicant: ASUSTeK COMPUTER INC.Inventor: Lin-Wei Chiu
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Publication number: 20250130256Abstract: A probe head includes an upper pin holder and a lower pin holder coupled to the upper pin holder. A pin arrangement space is defined between the upper pin holder and the lower pin holder. A conductive film is disposed between the upper pin holder and the lower pin holder. A plurality of probe pins penetrates through the upper pin holder, the conductor film and the lower pin holder, and extends outwardly from a bottom surface of the lower pin holder.Type: ApplicationFiled: October 3, 2024Publication date: April 24, 2025Applicant: MEDIATEK INC.Inventors: Jing-Hui Zhuang, Ying-Chou Shih, Chang-Lin Wei, Sheng-Wei Lei, Chih-Yang Liu, Jhih-Huei Chiu, Yen-Hui Li, Che-Sheng Lin
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Patent number: 12272554Abstract: A method of manufacturing semiconductor device includes forming a multilayer photoresist structure including a metal-containing photoresist over a substrate. The multilayer photoresist structure includes two or more metal-containing photoresist layers having different physical parameters. The metal-containing photoresist is a reaction product of a first precursor and a second precursor, and each layer of the multilayer photoresist structure is formed using different photoresist layer formation parameters. The different photoresist layer formation parameters are one or more selected from the group consisting of the first precursor, an amount of the first precursor, the second precursor, an amount of the second precursor, a length of time each photoresist layer formation operation, and heating conditions of the photoresist layers.Type: GrantFiled: July 27, 2023Date of Patent: April 8, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jia-Lin Wei, Ming-Hui Weng, Chih-Cheng Liu, Yi-Chen Kuo, Yen-Yu Chen, Yahru Cheng, Jr-Hung Li, Ching-Yu Chang, Tze-Liang Lee, Chi-Ming Yang
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Patent number: 12271113Abstract: Method of manufacturing semiconductor device includes forming photoresist layer over substrate. Forming photoresist layer includes combining first precursor and second precursor in vapor state to form photoresist material, wherein first precursor is organometallic having formula: MaRbXc, where M at least one of Sn, Bi, Sb, In, Te, Ti, Zr, Hf, V, Co, Mo, W, Al, Ga, Si, Ge, P, As, Y, La, Ce, Lu; R is substituted or unsubstituted alkyl, alkenyl, carboxylate group; X is halide or sulfonate group; and 1?a?2, b?1, c?1, and b+c?5. Second precursor is at least one of an amine, a borane, a phosphine. Forming photoresist layer includes depositing photoresist material over the substrate. The photoresist layer is selectively exposed to actinic radiation to form latent pattern, and the latent pattern is developed by applying developer to selectively exposed photoresist layer to form pattern.Type: GrantFiled: January 15, 2021Date of Patent: April 8, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Cheng Liu, Yi-Chen Kuo, Jia-Lin Wei, Ming-Hui Weng, Yen-Yu Chen, Jr-Hung Li, Yahru Cheng, Chi-Ming Yang, Tze-Liang Lee, Ching-Yu Chang
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Treatment agent for electronic-grade low-dielectric fiberglass cloth, and preparation method thereof
Patent number: 12241199Abstract: A treatment agent for an electronic-grade low-dielectric fiberglass cloth, and a preparation method thereof are provided. The treatment agent for an electronic-grade low-dielectric fiberglass cloth is prepared from the following raw materials in weight percentages: a coupling agent A: 0.6% to 1.2%, a coupling agent B: 0.3% to 0.8%, a coupling agent additive: 0.01% to 1.5%, an alcohol: 0.1% to 0.5%, an acid: 0.1% to 0.5%, and water: the balance, where the coupling agent A is a vinyl-containing coupling agent; the coupling agent B is a vinylbenzyl-containing coupling agent; and the coupling agent additive is a salt of a maleic anhydride (MA)-grafted copolymer. On the basis of meeting the low dielectric performance, the treatment agent of the present disclosure improves the binding performance of the low-dielectric fiberglass cloth to a low-dielectric customer resin and enhances the mechanical performance and heat resistance of the low-dielectric fiberglass cloth.Type: GrantFiled: May 7, 2022Date of Patent: March 4, 2025Assignee: TAISHAN FIBERGLASS ZOUCHENG CO., LTD.Inventors: Wei Li, Qiang Fang, Huaqing Xiao, Yingying Zhang, Dongfeng Liu, Siqi Niu, Lin Wei, Xiaochen Wang -
Publication number: 20240392393Abstract: The invention, in part, encompasses methods to assess viral infections in cells and subjects. The invention includes methods that can be used to determine the presence or absence of a viral infection in a cell or subject; severity of a viral infection in a cell or subject, and/or risk of a severe viral infection in a cell or subject. Certain methods of the invention also include selecting and/or administration a therapeutic regimen for a subject with a viral infection, based in part on the determination of the presence and/or severity of the viral infection in the subject.Type: ApplicationFiled: January 19, 2022Publication date: November 28, 2024Inventors: Chia-Lin Wei, Chew Yee NGAN, Chee-Hong WONG
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Publication number: 20240385523Abstract: Method of manufacturing semiconductor device includes forming photoresist layer over substrate. Forming photoresist layer includes combining first precursor and second precursor in vapor state to form photoresist material, wherein first precursor is organometallic having formula: MaRbXc, where M at least one of Sn, Bi, Sb, In, Te, Ti, Zr, Hf, V, Co, Mo, W, Al, Ga, Si, Ge, P, As, Y, La, Ce, Lu; R is substituted or unsubstituted alkyl, alkenyl, carboxylate group; X is halide or sulfonate group; and 1?a?2, b?1, c?1, and b+c?5. Second precursor is at least one of an amine, a borane, a phosphine. Forming photoresist layer includes depositing photoresist material over the substrate. The photoresist layer is selectively exposed to actinic radiation to form latent pattern, and the latent pattern is developed by applying developer to selectively exposed photoresist layer to form pattern.Type: ApplicationFiled: July 31, 2024Publication date: November 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Cheng LIU, Yi-Chen KUO, Jia-Lin WEI, Ming-Hui WENG, Yen-Yu CHEN, Jr-Hung LI, Yahru CHENG, Chi-Ming YANG, Tze-Liang LEE, Ching-Yu CHANG
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Publication number: 20240385514Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, including combining a first precursor and a second precursor in a vapor state to form a photoresist material, and depositing the photoresist material over the substrate. A protective layer is formed over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation through the protective layer to form a latent pattern in the photoresist layer. The protective layer is removed, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.Type: ApplicationFiled: July 26, 2024Publication date: November 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Hui WENG, Chen-Yu LIU, Chih-Cheng LIU, Yi-Chen KUO, Jia-Lin WEI, Yen-Yu CHEN, Jr-Hung LI, Yahru CHENG, Chi-Ming YANG, Tze-Liang LEE, Ching-Yu CHANG
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Patent number: 12135501Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, including combining a first precursor and a second precursor in a vapor state to form a photoresist material, and depositing the photoresist material over the substrate. A protective layer is formed over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation through the protective layer to form a latent pattern in the photoresist layer. The protective layer is removed, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.Type: GrantFiled: August 3, 2023Date of Patent: November 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Hui Weng, Chen-Yu Liu, Chih-Cheng Liu, Yi-Chen Kuo, Jia-Lin Wei, Yen-Yu Chen, Jr-Hung Li, Yahru Cheng, Chi-Ming Yang, Tze-Liang Lee, Ching-Yu Chang
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Publication number: 20240355623Abstract: A method of forming a pattern in a photoresist layer includes forming a photoresist layer over a substrate, and reducing moisture or oxygen absorption characteristics of the photoresist layer. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.Type: ApplicationFiled: July 2, 2024Publication date: October 24, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Chen KUO, Chih-Cheng LIU, Ming-Hui WENG, Jia-Lin WEI, Yen-Yu CHEN, Jr-Hung LI, Yahru CHENG, Chi-Ming YANG, Tze-Liang LEE, Ching-Yu CHANG
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Publication number: 20240336538Abstract: Disclosed herein is a biochar controlled release fertilizer composition. Various embodiments include biochar and one or more nutrients encapsulated in a biodegradable polymer composite. Further embodiments of the controlled release fertilizer composition include one or more of alginate, kaolin, and waste water sludge. The nutrients of the fertilizer may be released such as to be available at the time needed for crop growth while minimizing waste and potentially harmful environmental effects.Type: ApplicationFiled: July 21, 2022Publication date: October 10, 2024Inventors: Lin Wei, Zhisheng Cen, Cheng Zhang, Yajun Wu
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Publication number: 20240296268Abstract: A method includes tagging source PDK devices (SPDs) in a source-circuit design (SCD); generating a source design simulation database (SDSD) based on source design key performance indicator (KPI) simulation data of the SPDs in the SCD; generating a target process design kit (PDK) simulation database (TPSD) based on target design KPI simulation data of a plurality of target-PDK devices (TPDs); creating a matching table based on the SDSD and the TPSD; matching, based on the matching table, one or more TPDs from the TPSD with each SPD in the SDSD based on SPD KPIs; ranking the one or more TPDs matched from the TPSD with each SPD in the SDSD based on the SPD KPIs; and exchanging, based on a migration mapping table that includes a one-to-one relationship for TPDs to the SPDs in the SCD, one or more SPDs in the SCD with one-to-one relational TPDs.Type: ApplicationFiled: June 19, 2023Publication date: September 5, 2024Inventors: Fong-Yuan CHANG, Hui Yu LEE, Yu-Hao CHEN, Tian-Jian WU, Tien-Chien HUANG, Manjo Kumar ENUGULA, Yu-Lin WEI, Jyun-Hao CHANG
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Patent number: 12057315Abstract: A method of forming a pattern in a photoresist layer includes forming a photoresist layer over a substrate, and reducing moisture or oxygen absorption characteristics of the photoresist layer. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.Type: GrantFiled: May 31, 2023Date of Patent: August 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Chen Kuo, Chih-Cheng Liu, Ming-Hui Weng, Jia-Lin Wei, Yen-Yu Chen, Jr-Hung Li, Yahru Cheng, Chi-Ming Yang, Tze-Liang Lee, Ching-Yu Chang
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TREATMENT AGENT FOR ELECTRONIC-GRADE LOW-DIELECTRIC FIBERGLASS CLOTH, AND PREPARATION METHOD THEREOF
Publication number: 20240240388Abstract: A treatment agent for an electronic-grade low-dielectric fiberglass cloth, and a preparation method thereof are provided. The treatment agent for an electronic-grade low-dielectric fiberglass cloth is prepared from the following raw materials in weight percentages: a coupling agent A: 0.6% to 1.2%, a coupling agent B: 0.3% to 0.8%, a coupling agent additive: 0.01% to 1.5%, an alcohol: 0.1% to 0.5%, an acid: 0.1% to 0.5%, and water: the balance, where the coupling agent A is a vinyl-containing coupling agent; the coupling agent B is a vinylbenzyl-containing coupling agent; and the coupling agent additive is a salt of a maleic anhydride (MA)-grafted copolymer. On the basis of meeting the low dielectric performance, the treatment agent of the present disclosure improves the binding performance of the low-dielectric fiberglass cloth to a low-dielectric customer resin and enhances the mechanical performance and heat resistance of the low-dielectric fiberglass cloth.Type: ApplicationFiled: May 7, 2022Publication date: July 18, 2024Applicant: TAISHAN FIBERGLASS ZOUCHENG CO., LTD.Inventors: Wei LI, Qiang FANG, Huaqing XIAO, Yingying ZHANG, Dongfeng LIU, Siqi NIU, Lin WEI, Xiaochen WANG -
Patent number: 11892871Abstract: A host circuit includes a first clock generator, a first input output interface, a first communication interface, and a first processor. The first clock generator generates a first clock signal. The first processor outputs a trigger signal through the first input output interface, records a first clock count of the first clock generator at the same time, and outputs the first clock count through the first communication interface. A slave circuit includes a second clock generator, a second input output interface, a second communication interface, and a second processor. The second clock generator generates a second clock signal. When receiving the trigger signal, the second processor records a second clock count of the second clock generator, and calculates a time difference between the first clock signal and the second clock signal according to the first clock count and the second clock count.Type: GrantFiled: March 2, 2022Date of Patent: February 6, 2024Assignee: Realtek Semiconductor Corp.Inventors: Po-Lin Wei, Ching-Lung Chen
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Patent number: 11884706Abstract: The present invention relates to an immunomodulating peptide comprising an amino acid sequence as shown in SEQ ID NO:1. The present invention also discloses use of the immunomodulating peptide in the preparation of a drug or skin care product for promoting skin wound healing. The present invention provides a new immunomodulating peptide and use thereof, and discloses the mechanism of action of the immunomodulating peptide in promoting wound healing. The immunomodulating peptide is useful as a wounding healing polypeptide template.Type: GrantFiled: August 7, 2020Date of Patent: January 30, 2024Assignee: SOOCHOW UNIVERSITYInventors: Lin Wei, Yang Yang, Wei Xu
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Patent number: 11879934Abstract: A test kit for testing a device under test (DUT) includes a socket structure for containing the DUT, and a plunger assembly detachably coupled with the socket structure. The plunger assembly includes a multi-layered structure having at least an interposer substrate sandwiched by a top socket and a nest.Type: GrantFiled: May 3, 2022Date of Patent: January 23, 2024Assignee: MEDIATEK INC.Inventors: Jing-Hui Zhuang, Ying-Chou Shih, Sheng-Wei Lei, Chang-Lin Wei, Chih-Yang Liu, Che-Hsien Huang, Yi-Chieh Lin
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Patent number: 11830889Abstract: A low noise device includes an isolation feature in a substrate. The low noise device further includes a gate stack over a channel in the substrate, wherein the isolation feature is adjacent to the channel. The low noise device further includes a spacer surrounding a portion of the gate stack, wherein an edge of the gate stack is spaced from an edge of the isolation feature adjacent to the spacer by a distance ranging from a minimum spacing distance to about 0.3 microns (?m).Type: GrantFiled: July 23, 2021Date of Patent: November 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Victor Chiang Liang, Fu-Huan Tsai, Chi-Feng Huang, Yu-Lin Wei, Fang-Ting Kuo, Meng-Chang Ho
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Publication number: 20230375920Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, including combining a first precursor and a second precursor in a vapor state to form a photoresist material, and depositing the photoresist material over the substrate. A protective layer is formed over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation through the protective layer to form a latent pattern in the photoresist layer. The protective layer is removed, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.Type: ApplicationFiled: August 3, 2023Publication date: November 23, 2023Inventors: Ming-Hui WENG, Chen-Yu LIU, Chih-Cheng LIU, Yi-Chen KUO, Jia-Lin WEI, Yen-Yu CHEN, Jr-Hung LI, Yahru CHENG, Chi-Ming YANG, Tze-Liang LEE, Ching-Yu CHANG
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Patent number: 11822237Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, including combining a first precursor and a second precursor in a vapor state to form a photoresist material, and depositing the photoresist material over the substrate. A protective layer is formed over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation through the protective layer to form a latent pattern in the photoresist layer. The protective layer is removed, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.Type: GrantFiled: October 15, 2020Date of Patent: November 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Hui Weng, Chen-Yu Liu, Chih-Cheng Liu, Yi-Chen Kuo, Jia-Lin Wei, Yen-Yu Chen, Jr-Hung Li, Yahru Cheng, Chi-Ming Yang, Tze-Liang Lee, Ching-Yu Chang