Patents by Inventor Liyang Zhang

Liyang Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230290886
    Abstract: Semiconductor structures and manufacturing methods thereof. A semiconductor structure includes: a first epitaxial layer; a bonding layer, on first epitaxial layer and provided with a first through-hole exposing first epitaxial layer; a silicon substrate, on a side of bonding layer away from first epitaxial layer, first epitaxial layer and the silicon substrate being bonded through the bonding layer; a through-silicon-via, in silicon substrate, through-silicon-via communicating with first through-hole; a second epitaxial layer, on first epitaxial layer exposed by first through-hole; a first electrode, on a side of first epitaxial layer away from bonding layer, and electrically coupled with first epitaxial layer; a second electrode, on a side of second epitaxial layer away from first epitaxial layer, and electrically coupled with second epitaxial layer.
    Type: Application
    Filed: April 15, 2021
    Publication date: September 14, 2023
    Applicant: ENKRIS SEMICONDUCTOR, INC.
    Inventors: Kai Cheng, Liyang Zhang
  • Publication number: 20230290905
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure may include: a first epitaxial layer disposed on a substrate; a bonding layer disposed on the first epitaxial layer (where the bonding layer is provided with a first through-hole to expose the first epitaxial layer); a silicon substrate disposed on a side of the bonding layer away from the first epitaxial layer (where the first epitaxial layer is bonded to the silicon substrate by the bonding layer, the silicon substrate is provided with a through-silicon-via, and the through-silicon-via communicates with the first through-hole); a silicon device disposed on the silicon substrate; and a second epitaxial layer disposed on the first epitaxial layer exposed by the first through-hole. The present disclosure can improve the quality of the second epitaxial layer, and realize the integration of a silicon device and a III-V semiconductor device.
    Type: Application
    Filed: April 15, 2021
    Publication date: September 14, 2023
    Applicant: ENKRIS SEMICONDUCTOR, INC.
    Inventors: Kai Cheng, Liyang Zhang
  • Publication number: 20230203505
    Abstract: This invention pertains to mutant Cas9 nucleic acids and proteins for use in CRISPR/Cas endonuclease systems, and their methods of use. In particular, the invention pertains to an isolated mutant Cas9 protein, wherein the isolated mutant Cas9 protein is active in a CRISPR/Cas endonuclease system, wherein the CRISPR/Cas endonuclease system displays increased on-target editing activity relative to a wild-type CRISPR/Cas endonuclease system. The invention also includes isolated nucleic acids encoding mutant Cas9 proteins, ribonucleoprotein complexes and CRSPR/Cas endonuclease systems having mutant Cas9 proteins that display increased on-target editing activity relative to a wild-type CRISPR/Cas endonuclease system.
    Type: Application
    Filed: July 5, 2022
    Publication date: June 29, 2023
    Inventors: Nathaniel Hunter Roberts, Liyang Zhang, Christopher Anthony Vakulskas
  • Publication number: 20230207609
    Abstract: The present disclosure provides LED structures and manufacturing methods thereof, LED devices and manufacturing methods thereof. The LED structure includes a substrate, light emitting units, first electrodes and second electrodes, and the substrate is provided with grooves with different depths. A light emitting unit is disposed in each of the grooves and includes a first semiconductor layer, a light emitting layer on the first semiconductor layer and a second semiconductor layer on the light emitting layer; light emitting layers in grooves with different depths emit different colors. A first electrode and a second electrode in each groove, the first electrode is electrically connected with the first semiconductor layer, and the second electrode is electrically connected with the second semiconductor layer.
    Type: Application
    Filed: December 23, 2022
    Publication date: June 29, 2023
    Applicant: Enkris Semiconductor (Wuxi), Ltd.
    Inventors: Zhizhong Guo, Liyang Zhang
  • Publication number: 20230135471
    Abstract: The present invention pertains to ubiquitin polypeptide variants (Ubvs) having improved affinity for 53BP1 relative to 53 ubiquitin polypeptide or i53 ubiquitin polypeptide, wherein the resultant interaction between the Ubvs and 53BP1 promotes increased homology directed repair of DNA double-strand break sites. Methods of suppressing 53BP1 recruitment to DNA double-strand break sites, increasing homologous recombination, increasing gene targeting, and editing a gene in a cell using a CRISPR system are provided with the Ubvs. Compositions and kits of Ubvs are also provided.
    Type: Application
    Filed: September 24, 2022
    Publication date: May 4, 2023
    Inventors: Christopher Anthony Vakulskas, Nicole Mary Bode, Steve Ehren Glenn, Liyang Zhang
  • Publication number: 20230138679
    Abstract: The present disclosure concerns polynucleotides and amino acids of Acidaminococcus sp. Cas12a (Cpf1) and methods for their use for genome editing in eukaryotic cells.
    Type: Application
    Filed: July 26, 2022
    Publication date: May 4, 2023
    Inventors: Liyang Zhang, Christopher Anthony Vakulskas, Nicole Mary Bode, Michael Allen Collingwood, Kristin Renee Beltz, Mark Aaron Behlke
  • Publication number: 20230105081
    Abstract: Disclosed is a wafer susceptor. A groove bottom of the wafer susceptor is divided by a first dividing line passing through a center of a groove into a first region close to a center of the wafer susceptor and a second region away from the center of the wafer susceptor. The groove bottom includes a groove bottom surface and a convex structure formed on the groove bottom surface. An average height of the convex structure located in the second region is greater than that of the convex structure located in the first region. A design structure of the groove bottom of the wafer susceptor well matches a warped III-V group nitride wafer in an active region epitaxial process.
    Type: Application
    Filed: December 2, 2022
    Publication date: April 6, 2023
    Applicant: ENKRIS SEMICONDUCTOR, INC.
    Inventors: Kai CHENG, Liyang ZHANG
  • Publication number: 20230098865
    Abstract: Disclosed is a wafer susceptor. A groove bottom of the wafer susceptor is divided by a first dividing line passing through a center of a groove into a first region close to a center of the wafer susceptor and a second region away from the center of the wafer susceptor. The groove bottom includes a groove bottom surface and a convex structure formed on the groove bottom surface. An average height of the convex structure located in the second region is greater than that of the convex structure located in the first region. A design structure of the groove bottom of the wafer susceptor well matches a warped III-V group nitride wafer in an active region epitaxial process.
    Type: Application
    Filed: December 2, 2022
    Publication date: March 30, 2023
    Applicant: ENKRIS SEMICONDUCTOR, INC.
    Inventors: Kai CHENG, Liyang ZHANG
  • Publication number: 20230006091
    Abstract: This application provides semiconductor structures and methods of manufacturing the same. A semiconductor structure includes: an N-type semiconductor layer, a light emitting layer, and a P-type ion doped layer that are disposed from bottom to up, wherein the P-type ion doped layer comprises an activated region and non-activated regions located on two sides of the activated region, P-type doping ions in the activated region are activated, and P-type doping ions in the non-activated region are passivated. The layout of the activated region and the non-activated regions makes an LED include: a high-efficiency light emitting region and light emitting obstacle regions located on two sides of the high-efficiency light emitting region.
    Type: Application
    Filed: June 11, 2020
    Publication date: January 5, 2023
    Applicant: ENKRIS SEMICONDUCTOR, INC.
    Inventors: Dandan Zhu, Liyang Zhang, Kai Cheng
  • Publication number: 20220416129
    Abstract: Disclosed are an optoelectronic device and a preparation method thereof. The optoelectronic device includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence. The conductivity type of the first semiconductor layer is opposite to that of the second semiconductor layer, and the second semiconductor layer is provided with a layer of nano-diamond structure, and the nano-diamond structure has the same conductivity type as the second semiconductor layer. The method for preparing the optoelectronic device is used to make the optoelectronic device. In the present application, by providing a layer of nano-diamond structure in the second semiconductor layer, the absorption of UV light emitted by the active layer can be effectively avoided, and the beneficial effect of greatly improving the light extraction efficiency of the UV LED can be achieved.
    Type: Application
    Filed: August 29, 2022
    Publication date: December 29, 2022
    Applicant: ENKRIS SEMICONDUCTOR, INC.
    Inventors: Liyang ZHANG, Kai CHENG
  • Publication number: 20220416114
    Abstract: Provided is a method of manufacturing a semiconductor structure. The method includes: providing a substrate, where the substrate includes a plurality of component areas and peripheral areas surrounding the plurality of component areas; next, forming a sacrificial layer on each of the plurality of component areas, and forming a semiconductor active layer on the sacrificial layer and the substrate not covered with the sacrificial layer; patterning the semiconductor active layer to remove the semiconductor active layer on the peripheral areas so as to form a plurality of annular grooves which expose the sacrificial layer, such that the semiconductor active layer on each of the plurality of component areas is independent; afterwards, removing the sacrificial layer on each of the plurality of component areas through the annular grooves, such that the independent semiconductor active layer is separated from the substrate, where the independent semiconductor active layer forms a semiconductor structure.
    Type: Application
    Filed: December 13, 2019
    Publication date: December 29, 2022
    Applicant: ENKRIS SEMICONDUCTOR, INC.
    Inventors: Kai Cheng, Liyang Zhang
  • Patent number: 11447758
    Abstract: The present disclosure concerns polynucleotides and amino acids of Acidaminococcus sp. Cas12a (Cpf1) and methods for their use for genome editing in eukaryotic cells.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: September 20, 2022
    Assignee: INTEGRATED DNA TECHNOLOGIES, INC.
    Inventors: Liyang Zhang, Christopher Anthony Vakulskas, Nicole Mary Bode, Michael Allen Collingwood, Kristin Renee Beltz, Mark Aaron Behlke
  • Publication number: 20220246424
    Abstract: The present invention provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a substrate; forming an amorphous layer on the substrate, wherein the amorphous layer includes a plurality of patterns to expose part of the substrate; forming a metal nitride layer on the amorphous layer; removing the amorphous layer to form a plurality of cavities between the substrate and the metal nitride layer; removing the substrate to form the semiconductor structure. In the present invention, an amorphous layer is formed on the substrate, and a metal nitride layer is formed on the amorphous layer. The amorphous layer can inhibit slip or dislocation during epitaxial growth, thereby improving the quality of the metal nitride layer and improving the performance of the semiconductor structure, while the metal nitride layer can realize self-supporting.
    Type: Application
    Filed: April 26, 2020
    Publication date: August 4, 2022
    Applicant: ENKRIS SEMICONDUCTOR, INC.
    Inventors: Kai Cheng, Liyang Zhang
  • Patent number: 11393951
    Abstract: The present application provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a substrate on which at least one light guide groove is provided, the light guide groove penetrating the substrate; and a light emitting structure disposed on one side of the substrate, the light emitting structure including at least one set of a first electrode and a second electrode. The light guide groove at least corresponds to one set of a first electrode and a second electrode to prevent bad points. A wavelength conversion dielectric layer is filled into the light guide groove to avoid a coffee ring effect and achieve uniform and full-color light emission of a light emitting device. The semiconductor structure may further save manufacturing costs and prevent crosstalk between light emitted from various light emitting units.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: July 19, 2022
    Assignee: ENKRIS SEMICONDUCTOR, INC.
    Inventors: Liyang Zhang, Kai Cheng
  • Publication number: 20220115561
    Abstract: Disclosed are a light-emitting device, a template of the light-emitting device and preparation methods thereof. The template of the light-emitting device comprises a substrate; a GaN-based semiconductor layer and a mask layer provided on the substrate, where the mask layer comprises a plurality of mask openings provided at intervals, and the plurality of mask openings are filled with the GaN-based semiconductor layer; and a sacrificial layer provided on a surface of the GaN-based semiconductor layer away from the substrate and located in the plurality of mask openings provided at intervals.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Applicant: ENKRIS SEMICONDUCTOR, INC.
    Inventors: Kai CHENG, Liyang ZHANG
  • Publication number: 20220108890
    Abstract: Disclosed is a method for preparing a substrate relate to the field of semiconductors. The method comprises the following steps: S1, providing a reaction container in which a base substrate is mounted; S2, conducting a metal source into the reaction container, and forming a thin film layer on a surface of the base substrate, wherein a part of a surface of the base substrate is covered by the thin film layer, so that the base substrate is provided with an exposed surface that is not covered by the thin film layer; and S3, conducting a corrosive gas into the reaction container to form one or more recessed holes in at least a part of the exposed surface.
    Type: Application
    Filed: December 16, 2021
    Publication date: April 7, 2022
    Inventors: Liyang ZHANG, Kai CHENG
  • Patent number: 11201263
    Abstract: A surface roughening method includes the following steps: preparing a first epitaxial layer of a three-dimensional island shape growth over a light emitting structure; and preparing a discontinuous second epitaxial layer over the first epitaxial layer. The surface roughening method provided in the present application is simple and convenient, and improves the efficiency. In addition to the epitaxial growth process, it is not necessary to use an additional process such as wet etching, photonic crystal and other processes to further process the surface of the epitaxial layer, and the method may be implemented by means of one process in a same reaction equipment.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: December 14, 2021
    Assignee: ENKRIS SEMICONDUCTOR, INC.
    Inventors: Liyang Zhang, Kai Cheng
  • Publication number: 20210348144
    Abstract: Described herein are CAS12A mutants from Lachnospiraceae bacterium and methods for use thereof. These mutants have enhanced DNA cleavage activities at non-canonical TTTT protospacer adjacent motifs (PAM) compared to the wild-type enzyme.
    Type: Application
    Filed: April 30, 2021
    Publication date: November 11, 2021
    Inventors: Liyang Zhang, Christopher Anthony Vakulskas
  • Patent number: 10964843
    Abstract: An patterned Si substrate-based LED epitaxial wafer and a preparation method therefor, the LED epitaxial wafer comprising: a patterned Si substrate (1) and an Al2O3 coating (2) growing on the patterned Si substrate (1); sequentially growing on the Al2O3 coating (2) are a nucleating layer (3), a first buffer layer (4), a first insertion layer (5), a second buffer layer (6), a second insertion layer (7), an n-GaN layer (8), a quantum well layer (9), a p-GaN layer (10), an n-electrode (14) electrically connected to the n-GaN layer and a p-electrode (13) electrically connected to the p-GaN layer. The present invention is suitable for the preparation of large-sized LED epitaxial wafers. Furthermore, the crystal quality is improved, and the light extraction efficiency of the LED die is improved.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: March 30, 2021
    Assignee: ENKRIS SEMICONDUCTOR, INC
    Inventors: Liyang Zhang, Kai Cheng
  • Publication number: 20200243736
    Abstract: Provided are a semiconductor device and a fabrication method for the same. The semiconductor device includes a substrate, a bonding metal layer, a reflective layer, a first conductive layer, an active layer, a second conductive layer, a first electrode and a second electrode. The first electrode runs from one side of the substrate that is away from the bonding metal layer, successively through the substrate, the bonding metal layer, the reflective layer, the second conductive layer and the active layer, and extends to the first conductive layer, with the first electrode connected with the first conductive layer. The second electrode is provided on one side of the substrate away from the bonding metal layer. The semiconductor device has a structure where the second conductive layer is shared, which provides more homogeneous light emission and higher light extraction efficiency, eliminates the interference among pixel units.
    Type: Application
    Filed: January 12, 2017
    Publication date: July 30, 2020
    Inventor: Liyang Zhang