Patents by Inventor Lokesh Mohan Gupta

Lokesh Mohan Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11907543
    Abstract: Provided are a computer program product, system, and method for managing swappable data structures in a plurality of memory devices based on access counts of the data structures. Data structures indicated as swappable are updated less frequently than most frequently updated data structures. Data structures not indicated as swappable are maintained in a first level memory device and not moved to a second level memory device. The first level memory device has lower latency than the second level memory device. Access counts are maintained for the data structures stored in the first level memory device that are indicated as swappable. Data structures are selected in the first level memory device having lowest access counts. The selected data structures are removed from the first level memory device and retained in the second level memory device.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: February 20, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Beth Ann Peterson, Lokesh Mohan Gupta, Matthew G. Borlick, Matthew Richard Craig
  • Patent number: 11822482
    Abstract: Provided are a computer program product for managing tracks in a storage in a cache. An active track data structure indicates tracks in the cache that have an active status. An active bit in a cache control block for a track is set to indicate active for the track indicated as active in the active track data structure. In response to processing the cache control block, a determination is made, from the cache control block for the track, whether the track is active or inactive to determine processing for the cache control block.
    Type: Grant
    Filed: November 10, 2022
    Date of Patent: November 21, 2023
    Inventors: Lokesh Mohan Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos, Brian Anthony Rinaldi, Beth Ann Peterson, Matthew G. Borlick
  • Patent number: 11797448
    Abstract: A computer-implemented method, according to one embodiment, includes: in response to a determination that an available capacity of one or more buffers in a primary cache is not outside a predetermined range, using the one or more buffers in the primary cache to satisfy all incoming I/O requests. In response to a determination that the available capacity of the one or more buffers in the primary cache is outside the predetermined range, one or more buffers in a secondary cache are allocated, and the one or more buffers in the secondary cache are used to satisfy at least some of the incoming I/O requests.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: October 24, 2023
    Assignee: International Business Machines Corporation
    Inventors: Beth Ann Peterson, Kevin J. Ash, Lokesh Mohan Gupta, Warren Keith Stanley, Roger G. Hathorn
  • Patent number: 11768773
    Abstract: Provided are I/O request type specific cache directories in accordance with the present description. In one embodiment, by limiting track entries of a cache directory to a specific I/O request type, the size of the cache directory may be reduced as compared to general cache directories for I/O requests of all types, for example. As a result, look-up operations directed to such smaller size I/O request type specific cache directories may be completed in each directory more quickly. In addition, look-ups may frequently be successfully completed after a look-up of a single I/O request type specific cache directory, improving the speed of cache look-ups and providing a significant improvement in system performance. Other aspects and advantages are provided, depending upon the particular application.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: September 26, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gail Spear, Lokesh Mohan Gupta, Kevin J. Ash, Kyler A. Anderson
  • Patent number: 11762559
    Abstract: In one aspect of write sort management in accordance with the present disclosure, a write sort task related to write sorting a write list of data units to be destaged to storage, is assigned to a storage controller to improve the load balance among plural storage controllers. In one embodiment, available processing capacities of each of the storage controllers is determined by, for example, polling each of the storage controllers. A write sort task may then be assigned to a selected storage controller as a function of determined available processing capacities of each of the storage controllers to improve the load balance among the storage controllers. Other aspects and advantages are provided, depending upon the particular application.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: September 19, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian D. Hatfield, Lokesh Mohan Gupta, Matthew G. Borlick
  • Patent number: 11726913
    Abstract: Provided are a computer program product, system, and method for using track status information on active or inactive status of track to determine whether to process a host request on a fast access channel. A host request to access a target track is received on a first channel to the host. A determination is made as to whether the target track has active or inactive status. The target track has active status when at least one process currently maintains a lock on the target track that prevents access and the target track has inactive status when no process maintains a lock on the target track that prevents access. Fail is returned to the host to cause the host to resend the host request on a second channel in response to the target track having the active status. The first channel has lower latency than the second channel.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: August 15, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh Mohan Gupta, Beth Ann Peterson, Matthew G. Borlick
  • Patent number: 11720500
    Abstract: Provided are a computer program product, system, and method for determining status of tracks in storage cached in a cache for a host. A storage controller receives from the host a list of tracks for the host to access and determines whether the tracks in the list are available in the cache for immediate access. A response is returned to the host indicating the tracks as one of available in the cache for immediate access and not available in the cache for immediate access.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: August 8, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh Mohan Gupta, Beth Ann Peterson, Matthew G. Borlick, Matthew J. Kalos
  • Patent number: 11641349
    Abstract: Aspects of the present disclosure relate to encryption management. A determination can be made whether an encryption algorithm is at-risk. In response to determining that the encryption algorithm is at-risk, data protected by the encryption algorithm can be identified. A security action can then be executed on the data protected by the encryption algorithm.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: May 2, 2023
    Assignee: International Business Machines Corporation
    Inventors: Lokesh Mohan Gupta, Matthew G. Borlick, Mark Elliott Hack, Micah Robison
  • Patent number: 11620218
    Abstract: A computer-implemented method, according to one approach, includes: determining whether to satisfy an I/O request using a first tier of memory in a secondary cache by inspecting a bypass indication in response to determining that the input/output (I/O) request includes a bypass indication. The secondary cache is coupled to a primary cache and a data storage device. The secondary cache also includes the first tier of memory and a second tier of memory. Moreover, in response to determining to satisfy the I/O request using the first tier of memory in the secondary cache, the I/O request is satisfied using the first tier of memory in the secondary cache. The updated data is also destaged from the secondary cache to the data storage device in response to determining that data associated with the I/O request has been updated as the result of satisfying the I/O request using the secondary cache.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: April 4, 2023
    Assignee: International Business Machines Corporation
    Inventors: Lokesh Mohan Gupta, Edward Hsiu-Wei Lin, Beth Ann Peterson, Matthew G. Borlick
  • Patent number: 11620055
    Abstract: Provided are computer program product, system, and method for managing data structures in a plurality of memory devices that are indicated to demote after initialization of the data structures. Indication is made to data structures to demote after initialization from a first level memory device to a second level memory device. The first level memory device has lower latency than the second level memory device. In response to completing initialization of the data structures in the first level memory device, the data structures indicated to demote after initialization are copied from the first level memory device to the second level memory device and removing the data structures indicate to move after initialization from the first level memory device.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: April 4, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Beth Ann Peterson, Lokesh Mohan Gupta, Matthew Richard Craig, Matthew G. Borlick
  • Publication number: 20230073544
    Abstract: Provided are a computer program product, system, and method for determining status of tracks in storage cached in a cache for a host. A storage controller receives from the host a list of tracks for the host to access and determines whether the tracks in the list are available in the cache for immediate access. A response is returned to the host indicating the tracks as one of available in the cache for immediate access and not available in the cache for immediate access.
    Type: Application
    Filed: September 3, 2021
    Publication date: March 9, 2023
    Inventors: Lokesh Mohan Gupta, Beth Ann Peterson, Matthew G. Borlick, Matthew J. Kalos
  • Publication number: 20230075922
    Abstract: Provided are a computer program product for managing tracks in a storage in a cache. An active track data structure indicates tracks in the cache that have an active status. An active bit in a cache control block for a track is set to indicate active for the track indicated as active in the active track data structure. In response to processing the cache control block, a determination is made, from the cache control block for the track, whether the track is active or inactive to determine processing for the cache control block.
    Type: Application
    Filed: November 10, 2022
    Publication date: March 9, 2023
    Inventors: Lokesh Mohan Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos, Brian Anthony Rinaldi, Beth Ann Peterson, Matthew G. Borlick
  • Publication number: 20230070794
    Abstract: Provided are a computer program product, system, and method for using track status information on active or inactive status of track to determine whether to process a host request on a fast access channel. A host request to access a target track is received on a first channel to the host. A determination is made as to whether the target track has active or inactive status. The target track has active status when at least one process currently maintains a lock on the target track that prevents access and the target track has inactive status when no process maintains a lock on the target track that prevents access. Fail is returned to the host to cause the host to resend the host request on a second channel in response to the target track having the active status. The first channel has lower latency than the second channel.
    Type: Application
    Filed: September 3, 2021
    Publication date: March 9, 2023
    Inventors: Lokesh Mohan Gupta, Beth Ann Peterson, Matthew G. Borlick
  • Patent number: 11580022
    Abstract: In one aspect of write sort management in accordance with the present disclosure, a sort/no-sort determination is made prior to issuing to a write command to a target storage controller. The write command identifies a write data unit such track write data, for example, of a first write list of write data units to be written to storage locations of storage. The write command further identifies the storage location at which the write data unit of the first write list is to be stored. In one embodiment, the sort/no-sort determination determines whether an insertion point for an entry in a target write list is to be determined as a function of a write list search such as a logarithmic time search for a write list sort. As a result, the write list search for a write list sort, may be selectively either performed or bypassed for insertion of the target write list entry as a function of the sort/no-sort determination Other aspects and advantages are provided, depending upon the particular application.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: February 14, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian D. Hatfield, Lokesh Mohan Gupta, Matthew G. Borlick
  • Patent number: 11573709
    Abstract: Provided are a computer program product, system, and method for maintaining data structures in a virtual memory comprised of a plurality of heterogeneous memory devices. Access counts are maintained for a plurality of data structures stored in a first level memory device. A determination is made of data structures in the first level memory device having lowest access counts. The determined data structures are deleted from the first level memory device and retaining copies of the data structures in a second level memory device, wherein the first level memory device has lower latency than the second level memory device.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: February 7, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Beth Ann Peterson, Lokesh Mohan Gupta, Matthew Richard Craig, Matthew G. Borlick
  • Publication number: 20230036075
    Abstract: Provided are a computer program product, system, and method for indicating extents of tracks in mirroring queues based on information gathered on tracks in extents in cache. Extent information on an extent of tracks in a cache indicated in an active cache list is processed in response to destaging a track from the active cache list to add to a demote list used to determine tracks to remove from the cache. The extent information is related to a number of modified tracks in an extent destaged from the active cache list. The extent information for the extent is used to determine one of a plurality of mirroring queues to indicate the extent including modified tracks. A mirroring queue having a higher priority than another mirroring queue is processed at a higher rate to determine extents of tracks to mirror from the cache to the secondary storage.
    Type: Application
    Filed: October 7, 2022
    Publication date: February 2, 2023
    Inventors: Lokesh Mohan Gupta, Kevin J. Ash, Kyler A. Anderson, Matthew J. Kalos
  • Publication number: 20230036755
    Abstract: Provided are a computer program product for managing tracks in a storage in a cache. An active track data structure indicates tracks in the cache that have an active status. An active bit in a cache control block for a track is set to indicate active for the track indicated as active in the active track data structure. In response to processing the cache control block, a determination is made, from the cache control block for the track, whether the track is active or inactive to determine processing for the cache control block.
    Type: Application
    Filed: July 29, 2021
    Publication date: February 2, 2023
    Inventors: Lokesh Mohan Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos, Brian Anthony Rinaldi, Beth Ann Peterson, Matthew G. Borlick
  • Patent number: 11550726
    Abstract: Provided are a computer program product for managing tracks in a storage in a cache. An active track data structure indicates tracks in the cache that have an active status. An active bit in a cache control block for a track is set to indicate active for the track indicated as active in the active track data structure. In response to processing the cache control block, a determination is made, from the cache control block for the track, whether the track is active or inactive to determine processing for the cache control block.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: January 10, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh Mohan Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos, Brian Anthony Rinaldi, Beth Ann Peterson, Matthew G. Borlick
  • Patent number: 11494304
    Abstract: Provided are a computer program product, system, and method for indicating extents of tracks in mirroring queues based on information gathered on tracks in extents in cache. Extent information on an extent of tracks in a cache indicated in an active cache list is processed in response to destaging a track from the active cache list to add to a demote list used to determine tracks to remove from the cache. The extent information is related to a number of modified tracks in an extent destaged from the active cache list. The extent information for the extent is used to determine one of a plurality of mirroring queues to indicate the extent including modified tracks. A mirroring queue having a higher priority than another mirroring queue is processed at a higher rate to determine extents of tracks to mirror from the cache to the secondary storage.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: November 8, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh Mohan Gupta, Kevin J. Ash, Kyler A. Anderson, Matthew J. Kalos
  • Publication number: 20220334970
    Abstract: A computer-implemented method, according to one embodiment, includes: in response to a determination that an available capacity of one or more buffers in a primary cache is not outside a predetermined range, using the one or more buffers in the primary cache to satisfy all incoming I/O requests. In response to a determination that the available capacity of the one or more buffers in the primary cache is outside the predetermined range, one or more buffers in a secondary cache are allocated, and the one or more buffers in the secondary cache are used to satisfy at least some of the incoming I/O requests.
    Type: Application
    Filed: July 5, 2022
    Publication date: October 20, 2022
    Inventors: Beth Ann Peterson, Kevin J. Ash, Lokesh Mohan Gupta, Warren Keith Stanley, Roger G. Hathorn