Patents by Inventor Lokesh Mohan Gupta

Lokesh Mohan Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11169933
    Abstract: An indication of a maximum retention time in a cache comprising a first type of memory and a second type of memory for a first plurality of tracks is received from a host application, wherein no maximum retention time is indicated for a second plurality of tracks. In response to demoting a track of the first plurality of tracks from the first type of memory to the second type of memory, an adjustment of a first amount of time that the track is allowed to be retained in the second type of memory is based on a second amount of time the track has already been present in the first type of memory prior to being demoted from the first type of memory to the second type of memory.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: November 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh Mohan Gupta, Matthew G. Borlick, Kyler A. Anderson, Beth Ann Peterson
  • Patent number: 11163697
    Abstract: Provided are techniques for using a memory subsystem for a workload job. A section of a memory subsystem is allocated to a workload job, where the memory subsystem is comprised of a plurality of heterogeneous memory devices. In response to a track being modified for the workload job in a cache, it is determined that modified tracks have reached a threshold portion of the cache. In response to determining that the track exists in the section of the memory subsystem, data in the track in the section of the memory subsystem is overwritten with data in the track in the cache. in response to determining that the track does not exist in the section of the memory subsystem, the data in the track in the cache is copied to the track in the section of the memory subsystem, and the track is demoted from the cache.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: November 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh Mohan Gupta, Matthew G. Borlick, Kevin J. Ash, Kyler A. Anderson
  • Publication number: 20210334038
    Abstract: A method for improving destage performance to a RAID array is disclosed. In one embodiment, such a method periodically scans a cache for first strides that are ready to be destaged to a RAID array. While scanning the cache, the method identifies second strides that are not currently ready to be destaged to the RAID array, but will likely be ready to be destaged during a subsequent scan of the cache. The method initiates preemptive staging of any missing data of the second strides from the RAID array into the cache in preparation for the subsequent scan. Upon occurrence of the subsequent scan, the method destages, from the cache, the second strides from the cache to the RAID array. A corresponding system and computer program product are also disclosed.
    Type: Application
    Filed: April 22, 2020
    Publication date: October 28, 2021
    Applicant: International Business Machines Corporation
    Inventors: Lokesh Mohan Gupta, Clint A. Hardy, Brian Anthony Rinaldi, Karl Allen Nielsen
  • Publication number: 20210334036
    Abstract: In one aspect of multi-mode address mapping management in accordance with the present disclosure, mapping and unmapping operations may be conducted in one of multiple address mapping management modes to both improve overall system performance and maintain data integrity. In one embodiment, a first address mapping management mode such as a rigorous mode, for example, confirms completion of an unmapping of an address mapped data unit buffer before a re-mapping is permitted. Mapping and unmapping operations may be switched to a performance mode in which unmap completion confirmation is bypassed to improve performance. In one embodiment, address mapping management modes may be switched in real time as a function of monitored operating conditions. Other aspects and advantages are provided, depending upon the particular application.
    Type: Application
    Filed: April 24, 2020
    Publication date: October 28, 2021
    Inventors: Trung N. Nguyen, Kevin J. Ash, Brian Anthony Rinaldi, Lokesh Mohan Gupta, Kyler A. Anderson
  • Publication number: 20210334133
    Abstract: Provided are techniques for adjusting a dispatch ratio for dispatching tasks from multiple queues. The dispatch ratio is set for each queue of a plurality of queues. A number of Central Processing Unit (CPU) cycles used by tasks from each of the plurality of queues during the interval is tracked. A CPU high percentage is determined that indicates a percentage of CPU cycles used by high priority tasks. In response to determining that the CPU high percentage is below a high threshold, a new dispatch ratio is calculated that indicates an increased number of high priority tasks are to be dispatched, and the new dispatch ratio is based on the CPU high percentage, the high threshold, and a current dispatches high value. The increased number of high priority tasks are dispatched from the high priority queue based on the new dispatch ratio during a new interval.
    Type: Application
    Filed: April 27, 2020
    Publication date: October 28, 2021
    Inventors: Matthew Richard Craig, Matthew J. Kalos, Matthew G. Borlick, Micah Robison, Lokesh Mohan Gupta
  • Patent number: 11157199
    Abstract: In one aspect of multi-mode address mapping management in accordance with the present disclosure, mapping and unmapping operations may be conducted in one of multiple address mapping management modes to both improve overall system performance and maintain data integrity. In one embodiment, a first address mapping management mode such as a rigorous mode, for example, confirms completion of an unmapping of an address mapped data unit buffer before a re-mapping is permitted. Mapping and unmapping operations may be switched to a performance mode in which unmap completion confirmation is bypassed to improve performance. In one embodiment, address mapping management modes may be switched in real time as a function of monitored operating conditions. Other aspects and advantages are provided, depending upon the particular application.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: October 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Trung N. Nguyen, Kevin J. Ash, Brian Anthony Rinaldi, Lokesh Mohan Gupta, Kyler A. Anderson
  • Patent number: 11151058
    Abstract: Provided are a computer program product, system, and method for staging data from storage to a fast cache tier of a multi-tier cache in a non-adaptive sector caching mode in which data staged in response to a read request is limited to track sectors required to satisfy the read request. Data is also staged from storage to a slow cache tier of the multi-tier cache in a selected adaptive caching mode of a plurality of adaptive caching modes available for staging data of tracks. Adaptive caching modes are selected for the slow cache tier as a function of historical access ratios. Prestage requests for the slow cache tier are enqueued in one of a plurality of prestage request queues of various priority levels as a function of the selected adaptive caching mode and historical access ratios. Other aspects and advantages are provided, depending upon the particular application.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: October 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh Mohan Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew G. Borlick
  • Publication number: 20210318807
    Abstract: A storage controller is configured to perform a full stride destage, a strip destage, and an individual track destage. A machine learning module receives a plurality of inputs corresponding to a plurality of factors that affect performance of data transfer operations and preservation of drive life in the storage controller. In response to receiving the inputs, the machine learning module generates a first output, a second output, and a third output that indicate a preference measure for the full stride destage, the strip destage, and the individual track destage respectively.
    Type: Application
    Filed: April 14, 2020
    Publication date: October 14, 2021
    Inventors: Lokesh Mohan Gupta, Clint A. Hardy, Karl Allen Nielsen, Brian Anthony Rinaldi
  • Publication number: 20210318806
    Abstract: A first score corresponding to a full stride destage, a second score corresponding to a strip destage, and a third score corresponding to an individual track destage are computed, wherein the first score, the second score, and the third score are computed for a group of Input/Output (I/O) operations based on a first metric and a second metric, wherein the first metric is configured to affect a performance of data transfers, and wherein the second metric is configured to affect a drive life. A determination is made of a type of destage to perform based on the first score, the second score, and the third score.
    Type: Application
    Filed: April 14, 2020
    Publication date: October 14, 2021
    Inventors: Clint A. Hardy, Lokesh Mohan Gupta, Karl Allen Nielsen, Brian Anthony Rinaldi
  • Publication number: 20210286723
    Abstract: Provided are a computer program product, system, and method for indicating extents of tracks in mirroring queues based on information gathered on tracks in extents in cache. Extent information on an extent of tracks in a cache indicated in an active cache list is processed in response to destaging a track from the active cache list to add to a demote list used to determine tracks to remove from the cache. The extent information is related to a number of modified tracks in an extent destaged from the active cache list. The extent information for the extent is used to determine one of a plurality of mirroring queues to indicate the extent including modified tracks. A mirroring queue having a higher priority than another mirroring queue is processed at a higher rate to determine extents of tracks to mirror from the cache to the secondary storage.
    Type: Application
    Filed: March 13, 2020
    Publication date: September 16, 2021
    Inventors: Lokesh Mohan Gupta, Kevin J. Ash, Kyler A. Anderson, Matthew J. Kalos
  • Publication number: 20210286691
    Abstract: Provided are a computer program product, system, and method for using a mirroring cache list to mirror modified tracks for a primary storage in a cache to a secondary storage. Indication is made of a modified track for the primary storage stored in the cache in a mirroring cache list. The mirroring cache list is processed to select modified tracks in the cache to transfer to the secondary storage that have not yet been transferred. The selected modified tracks are transferred to the secondary storage. Indication of a modified track is removed from the mirroring cache list in response to demoting the modified track from the cache.
    Type: Application
    Filed: March 13, 2020
    Publication date: September 16, 2021
    Inventors: Lokesh Mohan Gupta, Kevin J. Ash, Kyler A. Anderson, Matthew J. Kalos
  • Publication number: 20210286729
    Abstract: Provided are a computer program product, system, and method for using mirroring cache list to demote modified tracks from cache A modified track for a primary storage stored in the cache to mirror to a secondary storage is indicated in a mirroring cache list. The mirroring cache list is processed to select modified tracks in the cache to transfer to the secondary storage that have not yet been transferred. The selected modified tracks in the cache are transferred to the secondary storage. The mirroring cache list is processed to determine modified tracks in the cache to demote from the cache.
    Type: Application
    Filed: March 13, 2020
    Publication date: September 16, 2021
    Inventors: Lokesh Mohan Gupta, Kevin J. Ash, Kyler A. Anderson, Matthew J. Kalos
  • Publication number: 20210279179
    Abstract: Provided are I/O request type specific cache directories in accordance with the present description. In one embodiment, by limiting track entries of a cache directory to a specific I/O request type, the size of the cache directory may be reduced as compared to general cache directories for I/O requests of all types, for example. As a result, look-up operations directed to such smaller size I/O request type specific cache directories may be completed in each directory more quickly. In addition, look-ups may frequently be successfully completed after a look-up of a single I/O request type specific cache directory, improving the speed of cache look-ups and providing a significant improvement in system performance. Other aspects and advantages are provided, depending upon the particular application.
    Type: Application
    Filed: March 3, 2020
    Publication date: September 9, 2021
    Inventors: Gail SPEAR, Lokesh Mohan GUPTA, Kevin J. ASH, Kyler A. ANDERSON
  • Publication number: 20210279174
    Abstract: A computer-implemented method, according to one approach, includes: receiving a stream of incoming I/O requests, all of which are satisfied using one or more buffers in a primary cache. However, in response to determining that the available capacity of the one or more buffers in the primary cache is outside a predetermined range: one or more buffers in the secondary cache are allocated. These one or more buffers in the secondary cache are used to satisfy at least some of the incoming I/O requests, while the one or more buffers in the primary cache are used to satisfy a remainder of the incoming I/O requests. Moreover, in response to determining that the available capacity of the one or more buffers in the primary cache is not outside the predetermined range: the one or more buffers in the primary cache are again used to satisfy all of the incoming I/O requests.
    Type: Application
    Filed: March 9, 2020
    Publication date: September 9, 2021
    Inventors: Beth Ann Peterson, Kevin J. Ash, Lokesh Mohan Gupta, Warren Keith Stanley, Roger G. Hathorn
  • Publication number: 20210263863
    Abstract: A computer-implemented method, according to one approach, includes: initiating an I/O request using a primary cache, where the I/O request includes supplemental information pertaining to an anticipated workload of the I/O request. Performance characteristics experienced by the primary cache while satisfying the I/O request are also evaluated. The supplemental information and the performance characteristics are further used to determine whether to satisfy a remainder of the I/O request using the secondary cache. In response to determining to satisfy a remainder of the I/O request using the secondary cache, the I/O request is demoted from the primary cache to the secondary cache, and a remainder of the I/O request is satisfied using the secondary cache. However, in response to determining to not satisfy a remainder of the I/O request using the secondary cache, a remainder of the I/O request is satisfied using the primary cache.
    Type: Application
    Filed: April 23, 2021
    Publication date: August 26, 2021
    Inventors: Beth Ann Peterson, Chung Man Fung, Lokesh Mohan Gupta, Kyler A. Anderson
  • Publication number: 20210258290
    Abstract: Aspects of the present disclosure relate to encryption management. A determination can be made whether an encryption algorithm is at-risk. In response to determining that the encryption algorithm is at-risk, data protected by the encryption algorithm can be identified. A security action can then be executed on the data protected by the encryption algorithm.
    Type: Application
    Filed: February 17, 2020
    Publication date: August 19, 2021
    Inventors: Lokesh Mohan Gupta, Matthew G. Borlick, Mark Elliott Hack, Micah Robison
  • Publication number: 20210255772
    Abstract: Provided are a computer program product, system, and method for using mirror path statistics in recalling extents to a primary storage system and a secondary storage system from a third storage system, A recall request is received to recall extents from the third storage that were migrated from the primary storage or the secondary storage to the third storage. A determination is made as to whether mirror paths used to migrate extents from the primary storage to the secondary storage exceed a degradation criteria. Commands are sent to cause the recall extents to be recalled from the third storage to both the primary storage and the secondary storage in response to determining that the mirror paths exceed the degradation criteria.
    Type: Application
    Filed: February 14, 2020
    Publication date: August 19, 2021
    Inventors: Edward Hsiu-Wei Lin, Lokesh Mohan Gupta, Clint A. Hardy
  • Publication number: 20210255964
    Abstract: An indication is received from a host application of a first minimum retention time in a cache comprising a first type of memory and a second type of memory for a first plurality of tracks, wherein the first minimum retention time is not indicated for a second plurality of tracks. Based on the first minimum retention time, a second minimum retention time is set for the first plurality of tracks for the first type of memory and a third minimum retention time is set for the first plurality of tracks for the second type of memory. A track of the first plurality of tracks is demoted from the first type of memory, in response to determining that the track is a least recently used (LRU) track in a LRU list of tracks in the first type of memory and the track has been in the first type of memory for a time that exceeds the second minimum retention time.
    Type: Application
    Filed: February 13, 2020
    Publication date: August 19, 2021
    Inventors: Lokesh Mohan Gupta, Matthew G. Borlick, Beth Ann Peterson, Kyler A. Anderson
  • Publication number: 20210255965
    Abstract: An indication of a maximum retention time in a cache comprising a first type of memory and a second type of memory for a first plurality of tracks is received from a host application, wherein no maximum retention time is indicated for a second plurality of tracks. In response to demoting a track of the first plurality of tracks from the first type of memory to the second type of memory, an adjustment of a first amount of time that the track is allowed to be retained in the second type of memory is based on a second amount of time the track has already been present in the first type of memory prior to being demoted from the first type of memory to the second type of memory.
    Type: Application
    Filed: February 13, 2020
    Publication date: August 19, 2021
    Inventors: Lokesh Mohan Gupta, Matthew G. Borlick, Kyler A. Anderson, Beth Ann Peterson
  • Publication number: 20210255967
    Abstract: Indications of a minimum retention time and a maximum retention time in a cache comprising a first type of memory and a second type of memory are received from a host application for a first plurality of tracks, wherein the minimum retention time or the maximum retention time are not indicated for a second plurality of tracks. In response to accessing a track of the first plurality of tracks, the minimum retention time is set for the track for the first type of memory, and the maximum retention time is set for the track for the second type of memory.
    Type: Application
    Filed: February 13, 2020
    Publication date: August 19, 2021
    Inventors: Lokesh Mohan Gupta, Kyler A. Anderson, Beth Ann Peterson, Matthew G. Borlick