Patents by Inventor Lokesh Mohan Gupta

Lokesh Mohan Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220334970
    Abstract: A computer-implemented method, according to one embodiment, includes: in response to a determination that an available capacity of one or more buffers in a primary cache is not outside a predetermined range, using the one or more buffers in the primary cache to satisfy all incoming I/O requests. In response to a determination that the available capacity of the one or more buffers in the primary cache is outside the predetermined range, one or more buffers in a secondary cache are allocated, and the one or more buffers in the secondary cache are used to satisfy at least some of the incoming I/O requests.
    Type: Application
    Filed: July 5, 2022
    Publication date: October 20, 2022
    Inventors: Beth Ann Peterson, Kevin J. Ash, Lokesh Mohan Gupta, Warren Keith Stanley, Roger G. Hathorn
  • Patent number: 11474941
    Abstract: A computer-implemented method, according to one approach, includes: receiving a stream of incoming I/O requests, all of which are satisfied using one or more buffers in a primary cache. However, in response to determining that the available capacity of the one or more buffers in the primary cache is outside a predetermined range: one or more buffers in the secondary cache are allocated. These one or more buffers in the secondary cache are used to satisfy at least some of the incoming I/O requests, while the one or more buffers in the primary cache are used to satisfy a remainder of the incoming I/O requests. Moreover, in response to determining that the available capacity of the one or more buffers in the primary cache is not outside the predetermined range: the one or more buffers in the primary cache are again used to satisfy all of the incoming I/O requests.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: October 18, 2022
    Assignee: International Business Machines Corporation
    Inventors: Beth Ann Peterson, Kevin J. Ash, Lokesh Mohan Gupta, Warren Keith Stanley, Roger G. Hathorn
  • Patent number: 11467772
    Abstract: A method for improving destage performance to a RAID array is disclosed. In one embodiment, such a method periodically scans a cache for first strides that are ready to be destaged to a RAID array. While scanning the cache, the method identifies second strides that are not currently ready to be destaged to the RAID array, but will likely be ready to be destaged during a subsequent scan of the cache. The method initiates preemptive staging of any missing data of the second strides from the RAID array into the cache in preparation for the subsequent scan. Upon occurrence of the subsequent scan, the method destages, from the cache, the second strides from the cache to the RAID array. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: October 11, 2022
    Assignee: International Business Machines Corporation
    Inventors: Lokesh Mohan Gupta, Clint A. Hardy, Brian Anthony Rinaldi, Karl Allen Nielsen
  • Patent number: 11436159
    Abstract: A computer-implemented method, according to one approach, includes: initiating an I/O request using a primary cache, where the I/O request includes supplemental information pertaining to an anticipated workload of the I/O request. Performance characteristics experienced by the primary cache while satisfying the I/O request are also evaluated. The supplemental information and the performance characteristics are further used to determine whether to satisfy a remainder of the I/O request using the secondary cache. In response to determining to satisfy a remainder of the I/O request using the secondary cache, the I/O request is demoted from the primary cache to the secondary cache, and a remainder of the I/O request is satisfied using the secondary cache. However, in response to determining to not satisfy a remainder of the I/O request using the secondary cache, a remainder of the I/O request is satisfied using the primary cache.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: September 6, 2022
    Assignee: International Business Machines Corporation
    Inventors: Beth Ann Peterson, Chung Man Fung, Lokesh Mohan Gupta, Kyler A. Anderson
  • Patent number: 11429736
    Abstract: Aspects of the present disclosure relate to encryption management. An indication of a data set to be tagged with an encryption tag is received. A location for the encryption tag is determined. The encryption tag is stored at the location, where the encryption tag includes an encryption status indicator specifying whether or not the data is encrypted and an encryption algorithm indicator specifying an encryption algorithm used to encrypt the data.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: August 30, 2022
    Assignee: International Business Machines Corporation
    Inventors: Lokesh Mohan Gupta, Matthew G. Borlick, Mark Elliott Hack, Micah Robison
  • Publication number: 20220191180
    Abstract: Aspects of the present disclosure relate to encryption management. A determination can be made whether an encryption algorithm is at-risk. In response to determining that the encryption algorithm is at-risk, data protected by the encryption algorithm can be identified. A security action can then be executed on the data protected by the encryption algorithm.
    Type: Application
    Filed: March 7, 2022
    Publication date: June 16, 2022
    Inventors: Lokesh Mohan Gupta, Matthew G. Borlick, Mark Elliott Hack, Micah Robison
  • Patent number: 11321234
    Abstract: Provided are a computer program product, system, and method for using mirroring cache list to demote modified tracks from cache A modified track for a primary storage stored in the cache to mirror to a secondary storage is indicated in a mirroring cache list. The mirroring cache list is processed to select modified tracks in the cache to transfer to the secondary storage that have not yet been transferred. The selected modified tracks in the cache are transferred to the secondary storage. The mirroring cache list is processed to determine modified tracks in the cache to demote from the cache.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: May 3, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh Mohan Gupta, Kevin J. Ash, Kyler A. Anderson, Matthew J. Kalos
  • Patent number: 11321201
    Abstract: Provided are a computer program product, system, and method for using a mirroring cache list to mirror modified tracks for a primary storage in a cache to a secondary storage. Indication is made of a modified track for the primary storage stored in the cache in a mirroring cache list. The mirroring cache list is processed to select modified tracks in the cache to transfer to the secondary storage that have not yet been transferred. The selected modified tracks are transferred to the secondary storage. Indication of a modified track is removed from the mirroring cache list in response to demoting the modified track from the cache.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: May 3, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh Mohan Gupta, Kevin J. Ash, Kyler A. Anderson, Matthew J. Kalos
  • Patent number: 11303618
    Abstract: Aspects of the present disclosure relate to encryption management. A determination can be made whether an encryption algorithm is at-risk. In response to determining that the encryption algorithm is at-risk, data protected by the encryption algorithm can be identified. A security action can then be executed on the data protected by the encryption algorithm.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: April 12, 2022
    Assignee: International Business Machines Corporation
    Inventors: Lokesh Mohan Gupta, Matthew G. Borlick, Mark Elliott Hack, Micah Robison
  • Patent number: 11281808
    Abstract: A portable handheld device receives from a central repository, information on a failed hardware component of a computational device, wherein the information includes an authentication code to permit access to the failed hardware component and a time window in which the failed hardware component is permitted to be accessed. The portable handheld device uses the authentication code to access the failed hardware component for repair or replacement during the time window.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: March 22, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Markus Navarro, Micah Robison, Matthew G. Borlick, Lokesh Mohan Gupta, John Charles Elliott
  • Publication number: 20220027267
    Abstract: A computer-implemented method, according to one approach, includes: determining whether to satisfy an I/O request using a first tier of memory in a secondary cache by inspecting a bypass indication in response to determining that the input/output (I/O) request includes a bypass indication. The secondary cache is coupled to a primary cache and a data storage device. The secondary cache also includes the first tier of memory and a second tier of memory. Moreover, in response to determining to satisfy the I/O request using the first tier of memory in the secondary cache, the I/O request is satisfied using the first tier of memory in the secondary cache. The updated data is also destaged from the secondary cache to the data storage device in response to determining that data associated with the I/O request has been updated as the result of satisfying the I/O request using the secondary cache.
    Type: Application
    Filed: October 5, 2021
    Publication date: January 27, 2022
    Inventors: Lokesh Mohan Gupta, Edward Hsiu-Wei Lin, Beth Ann Peterson, Matthew G. Borlick
  • Patent number: 11231855
    Abstract: A storage controller is configured to perform a full stride destage, a strip destage, and an individual track destage. A machine learning module receives a plurality of inputs corresponding to a plurality of factors that affect performance of data transfer operations and preservation of drive life in the storage controller. In response to receiving the inputs, the machine learning module generates a first output, a second output, and a third output that indicate a preference measure for the full stride destage, the strip destage, and the individual track destage respectively.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: January 25, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh Mohan Gupta, Clint A. Hardy, Karl Allen Nielsen, Brian Anthony Rinaldi
  • Patent number: 11226744
    Abstract: A first score corresponding to a full stride destage, a second score corresponding to a strip destage, and a third score corresponding to an individual track destage are computed, wherein the first score, the second score, and the third score are computed for a group of Input/Output (I/O) operations based on a first metric and a second metric, wherein the first metric is configured to affect a performance of data transfers, and wherein the second metric is configured to affect a drive life. A determination is made of a type of destage to perform based on the first score, the second score, and the third score.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: January 18, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Clint A. Hardy, Lokesh Mohan Gupta, Karl Allen Nielsen, Brian Anthony Rinaldi
  • Patent number: 11210237
    Abstract: Indications of a minimum retention time and a maximum retention time in a cache comprising a first type of memory and a second type of memory are received from a host application for a first plurality of tracks, wherein the minimum retention time or the maximum retention time are not indicated for a second plurality of tracks. In response to accessing a track of the first plurality of tracks, the minimum retention time is set for the track for the first type of memory, and the maximum retention time is set for the track for the second type of memory.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: December 28, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh Mohan Gupta, Kyler A. Anderson, Beth Ann Peterson, Matthew G. Borlick
  • Patent number: 11204802
    Abstract: Provided are techniques for adjusting a dispatch ratio for dispatching tasks from multiple queues. The dispatch ratio is set for each queue of a plurality of queues. A number of Central Processing Unit (CPU) cycles used by tasks from each of the plurality of queues during the interval is tracked. A CPU high percentage is determined that indicates a percentage of CPU cycles used by high priority tasks. In response to determining that the CPU high percentage is below a high threshold, a new dispatch ratio is calculated that indicates an increased number of high priority tasks are to be dispatched, and the new dispatch ratio is based on the CPU high percentage, the high threshold, and a current dispatches high value. The increased number of high priority tasks are dispatched from the high priority queue based on the new dispatch ratio during a new interval.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: December 21, 2021
    Assignee: International Business Machines Corporation
    Inventors: Matthew Richard Craig, Matthew J. Kalos, Matthew G. Borlick, Micah Robison, Lokesh Mohan Gupta
  • Patent number: 11204712
    Abstract: Provided are a computer program product, system, and method for using mirror path statistics in recalling extents to a primary storage system and a secondary storage system from a third storage system, A recall request is received to recall extents from the third storage that were migrated from the primary storage or the secondary storage to the third storage. A determination is made as to whether mirror paths used to migrate extents from the primary storage to the secondary storage exceed a degradation criteria. Commands are sent to cause the recall extents to be recalled from the third storage to both the primary storage and the secondary storage in response to determining that the mirror paths exceed the degradation criteria.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: December 21, 2021
    Assignee: International Business Machines Corporation
    Inventors: Edward Hsiu-Wei Lin, Lokesh Mohan Gupta, Clint A. Hardy
  • Patent number: 11182291
    Abstract: A computer-implemented method, according to one approach, includes: receiving an I/O request. In response to determining that the I/O request does not include a bypass indication, the I/O request is satisfied using a primary cache which is coupled to a data storage device and a secondary cache having SCM. In response to determining that the data associated with the I/O request has been updated as a result of satisfying the I/O request: the updated data is destaged from the primary cache to the data storage device, the updated data is copied to the secondary cache, and the updated data is demoted from the primary cache. Yet, in response to determining that the data associated with the I/O request has not been updated: the data associated with the I/O request is copied to the secondary cache, and the data associated with the I/O request is demoted from the primary cache.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: November 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh Mohan Gupta, Edward Hsiu-Wei Lin, Beth Ann Peterson, Matthew G. Borlick
  • Publication number: 20210357323
    Abstract: In one aspect of write sort management in accordance with the present disclosure, a sort/no-sort determination is made prior to issuing to a write command to a target storage controller. The write command identifies a write data unit such track write data, for example, of a first write list of write data units to be written to storage locations of storage. The write command further identifies the storage location at which the write data unit of the first write list is to be stored. In one embodiment, the sort/no-sort determination determines whether an insertion point for an entry in a target write list is to be determined as a function of a write list search such as a logarithmic time search for a write list sort. As a result, the write list search for a write list sort, may be selectively either performed or bypassed for insertion of the target write list entry as a function of the sort/no-sort determination Other aspects and advantages are provided, depending upon the particular application.
    Type: Application
    Filed: May 15, 2020
    Publication date: November 18, 2021
    Inventors: Brian D. HATFIELD, Lokesh Mohan GUPTA, Matthew G. BORLICK
  • Publication number: 20210357117
    Abstract: In one aspect of write sort management in accordance with the present disclosure, a write sort task related to write sorting a write list of data units to be destaged to storage, is assigned to a storage controller to improve the load balance among plural storage controllers. In one embodiment, available processing capacities of each of the storage controllers is determined by, for example, polling each of the storage controllers. A write sort task may then be assigned to a selected storage controller as a function of determined available processing capacities of each of the storage controllers to improve the load balance among the storage controllers. Other aspects and advantages are provided, depending upon the particular application.
    Type: Application
    Filed: May 15, 2020
    Publication date: November 18, 2021
    Inventors: Brian D. HATFIELD, Lokesh Mohan GUPTA, Matthew G. BORLICK
  • Patent number: 11176057
    Abstract: An indication is received from a host application of a first minimum retention time in a cache comprising a first type of memory and a second type of memory for a first plurality of tracks, wherein the first minimum retention time is not indicated for a second plurality of tracks. Based on the first minimum retention time, a second minimum retention time is set for the first plurality of tracks for the first type of memory and a third minimum retention time is set for the first plurality of tracks for the second type of memory. A track of the first plurality of tracks is demoted from the first type of memory, in response to determining that the track is a least recently used (LRU) track in a LRU list of tracks in the first type of memory and the track has been in the first type of memory for a time that exceeds the second minimum retention time.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: November 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh Mohan Gupta, Matthew G. Borlick, Beth Ann Peterson, Kyler A. Anderson