Patents by Inventor Long Lu

Long Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11302594
    Abstract: A semiconductor package includes a substrate, an electronic component and a first dilatant layer. The electronic component is disposed on the substrate. The electronic component has a top surface, a bottom surface opposite to the top surface and a lateral surface extending between the top surface and the bottom surface. The first dilatant layer is disposed on the top surface of the electronic component and extends along the lateral surface of the electronic component.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: April 12, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Publication number: 20220104496
    Abstract: Compounds of formula I A-B??(I), wherein A is a radical selected from the group consisting of formulae A1 to A8: wherein the arrow denotes the point of attachment to the radical B; and B is a radical selected from the group consisting of formulae B1 to B11: wherein the arrow denotes the point of attachment to the radical A; and wherein the substituents are as defined in claim 1, and the agrochemically acceptable salts and all stereoisomers and tautomeric forms of the compounds of formula I can be used as insecticides and can be prepared in a manner known per se.
    Type: Application
    Filed: December 15, 2021
    Publication date: April 7, 2022
    Applicant: SYNGENTA PARTICIPATIONS AG
    Inventors: Andrew EDMUNDS, Michel MUEHLEBACH, Andre STOLLER, Olivier LOISELEUR, Anke BUCHHOLZ, Ottmar Franz HUETER, Roger Graham HALL, Daniel EMERY, Pierre Joseph Marcel JUNG, Long LU, Yaming WU, Aurelien BIGOT, Ruifang CHEN
  • Patent number: 11296002
    Abstract: A semiconductor device package includes a substrate, a first electronic component and a first encapsulant. The substrate has a first surface and a second surface opposite to the first surface. The first electronic component is disposed on the first surface of the substrate. The first encapsulant is disposed on the first surface of the substrate and covers the first electronic component. The first encapsulant has a first surface facing away the first surface of the substrate and includes a recess at an edge of the first surface of the first encapsulant.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: April 5, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 11271312
    Abstract: A semiconductor device package includes a circuit layer and a first antenna structure. The circuit layer includes a first surface, and a second surface opposite to the first surface. The first antenna structure is disposed on the first surface and electrically connected to the circuit layer. The first antenna structure includes a first patch, a second patch, a third patch, a first dielectric layer and a second dielectric layer. The second patch is disposed on the first patch. The first dielectric layer has a first dielectric constant (Dk), and is disposed between the first patch and the second patch. The third patch is disposed on the second patch. The second dielectric layer has a second dielectric constant and is disposed between the second patch and the third patch. The first dielectric constant is smaller than the second dielectric constant.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: March 8, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Publication number: 20220068781
    Abstract: A wiring structure and a method for manufacturing the same are provided. The wiring structure includes a conductive structure and a plurality of conductive through vias. The conductive structure includes a dielectric layer, a circuit layer in contact with the dielectric layer, a plurality of dam portions and an outer metal layer. The dam portions extend through the dielectric layer. The dam portion defines a through hole. The outer metal layer is disposed adjacent to a top surface of the dielectric layer and extends into the through hole of the dam portion. The conductive through vias are disposed in the through holes of the dam portions and electrically connecting the circuit layer.
    Type: Application
    Filed: August 28, 2020
    Publication date: March 3, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen-Long LU
  • Publication number: 20220052024
    Abstract: A semiconductor device package and a method of manufacturing the same are provided. The semiconductor device package includes a first module, a second module, a first intermediate circuit layer, a first conductive transmission path and a second conductive transmission path. The second module is stacked on the first module. The first intermediate circuit layer is arranged between the first module and the second module. The first conductive transmission is configured to electrically connect the first semiconductor module with the first intermediate circuit layer. The second conductive transmission path is configured to electrically connect the first intermediate circuit layer with the second semiconductor module.
    Type: Application
    Filed: August 14, 2020
    Publication date: February 17, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen-Long LU
  • Patent number: 11239174
    Abstract: A semiconductor package structure includes a first semiconductor die, a second semiconductor die, a third semiconductor die and an external contact. The second semiconductor die is disposed adjacent to the first semiconductor die. The third semiconductor die electrically connects the first semiconductor die and the second semiconductor die. The external contact is electrically connected to the third semiconductor die. An electrical path between the third semiconductor die and the external contact extends through a space between the first semiconductor die and the second semiconductor die.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: February 1, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 11229208
    Abstract: Compounds of formula I A-B??(I), wherein A is a radical selected from the group consisting of formulae A1 to A8: wherein the arrow denotes the point of attachment to the radical B; and B is a radical selected from the group consisting of formulae B1 to B11: wherein the arrow denotes the point of attachment to the radical A; and wherein the substituents are as defined in claim 1, and the agrochemically acceptable salts and all stereoisomers and tautomeric forms of the compounds of formula I can be used as insecticides and can be prepared in a manner known per se.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: January 25, 2022
    Assignee: SYNGENTA PARTICIPATIONS AG
    Inventors: Andrew Edmunds, Michel Muehlebach, André Stoller, Olivier Loiseleur, Anke Buchholz, Ottmar Franz Hueter, Aurelien Bigot, Roger Graham Hall, Daniel Emery, Pierre Joseph Marcel Jung, Long Lu, Yaming Wu, Ruifang Chen
  • Publication number: 20220016145
    Abstract: The present invention provides compositions and methods of their use in treating muscular dystrophy and other disorders.
    Type: Application
    Filed: April 5, 2021
    Publication date: January 20, 2022
    Inventors: Qi Long LU, Marcela CATALDI, Pei Juan LU
  • Patent number: 11222870
    Abstract: A semiconductor device package includes a first substrate and a second substrate arranged above the first substrate. A first connector is disposed on the first substrate, and a first conductor passes through the second substrate and connects to the first connector.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: January 11, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen-Long Lu, Min Lung Huang
  • Patent number: 11217520
    Abstract: A wiring structure includes a first dielectric layer, a first circuit layer, a second dielectric layer and a conductive via. The first dielectric layer defines at least one through hole. The first circuit layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the first dielectric layer to cover the first circuit layer, wherein a first portion of the second dielectric layer is disposed in the through hole of the first dielectric layer. The conductive via extends through the first portion of the second dielectric layer in the through hole of the first dielectric layer, and is electrically isolated from the first circuit layer.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: January 4, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 11215762
    Abstract: An optical device package includes a semiconductor substrate, and an optical device. The semiconductor substrate has a first surface, a second surface different in elevation from the first surface, and a profile connecting the first surface to the second surface. A surface roughness of the profile is greater than a surface roughness of the second surface. The optical device is disposed on the second surface and surrounded by the profile.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: January 4, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Huang-Hsien Chang, Po Ju Wu, Yu Cheng Chen, Wen-Long Lu
  • Patent number: 11189587
    Abstract: A semiconductor device package includes an electronic component. The electronic component has an active surface, a back surface opposite to the active surface, and a lateral surface connected between the active surface and the back surface. The electronic component has an electrical contact disposed on the active surface. The semiconductor device package also includes a redistribution layer (RDL) contacting the back surface of the electronic component, a first dielectric layer surrounding the electrical contact on the active surface of the electronic component, and a second dielectric layer surrounding the lateral surface of the electronic component and the first dielectric layer. The second dielectric layer has a first sidewall in contact with the lateral surface of the electronic component and a second sidewall opposite to the first sidewall. The second sidewall of the second dielectric layer has a first portion proximal to the RDL and a second portion distal from the RDL.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: November 30, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 11177552
    Abstract: A semiconductor device package includes a dielectric layer and a stacking conductive structure. The dielectric layer includes a first surface. The stacking conductive structure is disposed on the first surface of the dielectric layer. The stacking conductive structure includes a first conductive layer disposed on the first surface of the dielectric layer, and a second conductive layer stacked on the first conductive layer. A first surface roughness of the first surface of the dielectric layer is larger than a second surface roughness of a top surface of the first conductive layer, and the second surface roughness of the top surface of the first conductive layer is larger than a third surface roughness of a top surface of the second conductive layer.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: November 16, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Publication number: 20210341480
    Abstract: Saliva-based testing for viruses including SARS-CoV-2 are provided. Simple collection methods allow for at-home collection, reducing the risk and burden on healthcare workers using conventional testing methods. Tests can quantitatively analyze both viral nucleic acids to assess viral load as well as virus-specific antibodies to track disease progression and potential immunity.
    Type: Application
    Filed: April 29, 2021
    Publication date: November 4, 2021
    Inventors: Shi-Long Lu, Brian L. Harry, Jose P. Zevallos, Robert E. Blomquist, Xin Yao, Yue Qiu, Marsha T. Tharakan
  • Publication number: 20210335729
    Abstract: A semiconductor package device includes a wiring structure, a semiconductor chip and an encapsulant. The semiconductor chip is electrically connected to the wiring structure. The encapsulant is disposed on the wiring structure and covers the semiconductor chip. A roughness (Ra) of a surface of the encapsulant is about 5 nm to about 50 nm.
    Type: Application
    Filed: July 6, 2021
    Publication date: October 28, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen-Long LU
  • Patent number: 11158572
    Abstract: A package structure includes a base material, at least one electronic device, at least one dummy pillar and an encapsulant. The electronic device is electrically connected to the base material. The dummy pillar is disposed on the base material. The encapsulant covers the electronic device and a top end of the dummy pillar.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: October 26, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 11139247
    Abstract: An interconnection structure includes a first dielectric layer and a second dielectric layer. The second dielectric layer is disposed on the first dielectric layer. The second dielectric layer has a first surface and a second surface, both facing toward the first dielectric layer. The first surface of the second dielectric layer is recessed from the second surface of the second dielectric layer and defines a recess. A portion of the first dielectric layer is disposed within the recess.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: October 5, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Publication number: 20210296267
    Abstract: A semiconductor device and method for manufacturing the same are provided. The method includes providing a first substrate. The method also includes forming a first metal layer on the first substrate. The first metal layer includes a first metal material. The method further includes treating a first surface of the first metal layer with a solution including an ion of a second metal material. In addition, the method includes forming a plurality of metal particles including the second metal material on a portion of the first surface of the first metal layer.
    Type: Application
    Filed: March 20, 2020
    Publication date: September 23, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jhao-Cheng CHEN, Huang-Hsien CHANG, Wen-Long LU, Shao Hsuan CHUANG, Ching-Ju CHEN, Tse-Chuan CHOU
  • Patent number: 11110144
    Abstract: Wolfberry glycopeptide composition and methods for preparing and using the same, the part with a molecular weight distribution of 1000 Da to 10000 Da of the wolfberry glycopeptide accounts for 50-85% on the HPLC differential refractive index map; and the protein content is 20-35% weight percentage, neutral polysaccharide content is 20-35% weight percentage. Optionally, the uronic acid content is 5-20% weight percentage. The preparation method of the present invention removes part of insoluble impurities by a heating flocculation method, instead of the conventional organic solvent extraction process, and without using any organic solvents in the whole process.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: September 7, 2021
    Assignee: Shanghai Institute of Organic Chemistry, Chinese Academy of Sciences
    Inventors: Long Lu, Yan Jiang, Juan Shen, Zhigang Ding, Yuhua Xiang, Guiqing Chen, Gengyuan Tian