Patents by Inventor Mahesh

Mahesh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190050305
    Abstract: The present disclosure includes apparatuses comprising replaceable memory. An example apparatus may include a controller and a memory package coupled to the controller and including a plurality of memory dies. At least one of the memory package and the controller may be a replaceable unit that is removable from the apparatus and replaceable with a different replaceable unit while maintaining operation of the apparatus.
    Type: Application
    Filed: August 8, 2017
    Publication date: February 14, 2019
    Inventors: Ananda C. S. Mahesh, Gregory P. Shogan
  • Publication number: 20190051015
    Abstract: In one example a management system for an autonomous vehicle, comprises a first image sensor to collect first image data in a first geographic region proximate the autonomous vehicle and a second image sensor to collect second image data in a second geographic region proximate the first geographic region and a controller communicatively coupled to the first image sensor and the second image sensor and comprising processing circuitry to collect the first image data from the first image sensor and second image data from the second image sensor, generate a first reliability index for the first image sensor and a second reliability index for the second image sensor, and determine a correlation between the first image data and the second image data. Other examples may be described.
    Type: Application
    Filed: January 12, 2018
    Publication date: February 14, 2019
    Applicant: Intel Corporation
    Inventors: David Gonzalez Aguirre, Omar Florez, Julio Zamora Esquivel, Mahesh Subedar, Javier Felip Leon, Rebecca Chierichetti, Andrea Johnson, Glen Anderson
  • Publication number: 20190053161
    Abstract: A computing device may include an accessory radio that facilitates point-to-point wireless connectivity between the computing device and one or more accessory devices. The accessory radio may periodically broadcast its presence to the one or more accessory devices while operating in an active state. The accessory radio may transition from the active state to a sleep state after a period of inactivity. The computing device may also include a general purpose radio that may facilitate general wireless connectivity between the computing device and other devices. The general purpose radio may listen for any messages that are intended for the accessory radio while the accessory radio is in the sleep state. The general purpose radio may activate the accessory radio in response to the general purpose radio receiving a message, while the accessory radio is in the sleep state, that satisfies at least one activation condition.
    Type: Application
    Filed: August 9, 2017
    Publication date: February 14, 2019
    Inventors: Srinivasa L. RAO, Dong Hee PI, Mahesh YADAV, Joseph Michael SCHAEFER
  • Publication number: 20190050362
    Abstract: Herein is disclosed an integrated input/output (“I/O”) processing system, comprising an I/O port, configured to receive I/O data and to deliver the I/O data to one or more processors; one or more processors, further comprising a first processing logic and a second processing logic, wherein the one or more processors are configured to deliver the received I/O data to the first processing logic and to the second processing logic, and wherein the first processing logic and the second processing logic are configured to redundantly process the I/O data; and a comparator, configured to compare an output of the first processing logic and an output of the second processing logic.
    Type: Application
    Filed: June 21, 2018
    Publication date: February 14, 2019
    Inventors: Swadesh CHOUDHARY, Bahaa FAHIM, Mahesh WAGH
  • Publication number: 20190046313
    Abstract: The disclosure relates to voice prosthesis device that enables a laryngectomy patient to speak. The voice prosthesis device has a cylinder including a first end and a second end. An inner washer is attached to the first end and an outer washer is attached to the second end. A partial shutter is coupled to the first end of the cylinder. A shutter guard is placed at the inner part of the inner washer and is fixed to the cylinder. The device further includes plurality of rings. The partial shutter is made of platinum cured silicon and opens relatively to allow exhaled air to pass from the second end to the first end and prevents entry of food particles into the second end.
    Type: Application
    Filed: October 19, 2016
    Publication date: February 14, 2019
    Inventors: Vishal Uchila Shishir Rao, Shashank Mahesh
  • Patent number: 10204002
    Abstract: A method, article of manufacture, and apparatus for maintaining a cache index inside a deduplicated storage system is discussed. A determination is made to flush a cache buffer to the cache index, wherein both the cache buffer and the cache index comprise a plurality of cache buckets, wherein the cache buckets are stored on a plurality of logical data blocks. A write is initiated to at least one of the plurality of logical data blocks, wherein the write comprises at least one of the cache buckets. An error is received in response to the write request. The error is stored in a memory on the deduplicated storage system.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: February 12, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Satish Visvanathan, Mahesh Kamat, Rahul B Ugale, Ganesh Karuppur Rajagopalan
  • Patent number: 10203938
    Abstract: An example device may include one or more processors to receive an input associated with developing an application; determine a feature that may be included in the application based on the input; select an application programming interface (API) from an API repository, where the API may be associated with the feature of the application; select a user interface (UI) to facilitate user interaction with the application based on the API; and/or perform an action associated with developing the application.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: February 12, 2019
    Assignee: Accenture Global Solutions Limited
    Inventors: Pramodsing Bijani, Mahesh Bandkar, Anand Parulkar, Ravi Sachdev, Mufaddal Moazam Kantawala
  • Publication number: 20190039958
    Abstract: Hexagonal Boron Nitride (hBN) is a synthetic material that may be used in several applications due to its chemical inertness, thermal stability, and other beneficial properties. hBN composite materials and method for making such composites are described here. In particular composite materials including both functionalized hBN and cement or cementitious materials and methods for making the same are discussed. Such materials may be useful for construction, well cementing (both primary and remedial cementing), nuclear industry, 3D printing of advanced multifunctional composites, and refractory materials.
    Type: Application
    Filed: August 6, 2018
    Publication date: February 7, 2019
    Applicant: C-CRETE TECHNOLOGIES, LLC
    Inventors: Rouzbeh Shahsavari, Mahesh Bhatt
  • Publication number: 20190041895
    Abstract: A processing device includes a package, a plurality of dies disposed on the package, where each die comprises a clock receiver, and a single common clock source to generate a common clock signal. The processing device also includes a clock distribution circuitry coupled to the single common clock source. The clock distribution circuitry distributes the common clock signal from the single common clock source to each of the plurality of dies individually. The clock distribution circuitry includes a first group of terminated transmission lines. The first group of terminated transmission lines includes a first terminated transmission line, a second terminated transmission line, and a first termination resistor coupled between the first terminated transmission line and the second terminated transmission line. The first terminated transmission line and the second terminated transmission line receive the common clock signal from the single common clock source.
    Type: Application
    Filed: April 12, 2018
    Publication date: February 7, 2019
    Inventors: Yingyu Miao, Gerald Pasdast, Peipei Wang, Mahesh Kumashikar
  • Publication number: 20190042461
    Abstract: A processing device includes a core to execute instructions, and memory management circuitry coupled to, memory, the core and an I/O device that supports page faults. The memory management circuitry includes an express invalidations circuitry, and a page translation permission circuitry. The memory management circuitry is to, while the core is executing the instructions, receive a command to pause communication between the I/O device and the memory. In response to receiving the command to pause the communication, modify permissions of page translations by the page translation permission circuitry and transmit an invalidation request, by the express invalidations circuitry to the I/O device, to cause cached page translations in the I/O device to be invalidated.
    Type: Application
    Filed: April 20, 2018
    Publication date: February 7, 2019
    Inventors: Rupin Vakharwala, Amin Firoozshahian, Stephen Van Doren, Rajesh Sankaran, Mahesh Madhav, Omid Azizi, Andreas Kleen, Mahesh Maddury, Ashok Raj
  • Publication number: 20190043782
    Abstract: An integrated circuit package may include one or more integrated circuit dies and reconfigurable constrained vapor bubble (CVB) heat pipe structures formed on the integrated circuit dies. The reconfigurable CVB heat pipe structures may be adjusted using micro-electro-mechanical systems (MEMS) switches. By turning on a MEMS switch, the corresponding heat pipe structure will exhibit a first heat transfer efficiency. By turning off a MEMS switch, the corresponding heat pipe structure will exhibit a second heat transfer efficiency that is less than the first heat transfer efficiency. The reconfigurable CVB heat pipe structures may be statically programmed and/or dynamically adjusted as hot spot locations within the integrated circuit package migrate over time.
    Type: Application
    Filed: May 16, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Sumita Basu, Aravind Dasu, Mahesh A. Iyer
  • Publication number: 20190043204
    Abstract: An example apparatus for tracking features in image data includes an image data receiver to receive initial image data corresponding to an image from a camera and store the image data a circular buffer. The apparatus also includes a feature detector to detect features in the image data. The apparatus further includes a feature sorter to sort the detected features to generate sorted feature points. The apparatus includes a feature tracker to track the sorted feature points in subsequent image data corresponding to the image received at the image data receiver. The subsequent image data is to replace the initial image data in the circular buffer.
    Type: Application
    Filed: January 8, 2018
    Publication date: February 7, 2019
    Applicant: Intel IP Corporation
    Inventors: Dipan Kumar Mandal, Nagadastagiri Reddy C., Mahesh Mamidipaka, Om J. Omer
  • Publication number: 20190044825
    Abstract: A method and a system for determining and preventing outages in an IT network by predicting status, utilization, performance, or a combination thereof for IT resources is disclosed. The method includes extracting and classifying data for one or more parameters associated with a plurality of nodes. A set of historical metrics and real-time metrics are used for predicting status score, utilization score, and performance score of IT infrastructure resources. The predictions are compared with a predetermined threshold limit for identifying potential outage in the network. A summary indicating the predictions are displayed to an administrator for preventing and mitigating the potential downtime.
    Type: Application
    Filed: May 11, 2018
    Publication date: February 7, 2019
    Applicant: GAVS Technologies Pvt. Ltd.
    Inventors: MURALEEDHARAN VIJAYAKUMAR, VEERAMANIKANDAN PANDIARAJ, MAHESH MARIMUTHU, GOVINDARAJ MUNIYANDI
  • Publication number: 20190044518
    Abstract: A method of handling integrated circuit dies with defects is provided. After forming a plurality of dies on one or more silicon wafers, test equipment may be used to identify defects on the dies and to create corresponding defect maps. The defect maps can be combined to form an aggregate defect map. Circuit design tools may create keep-out zones from the aggregate defect map and run learning experiments on each die, while respecting the keep-out zones, to compute design metrics. The circuit design tools may further create larger keep-out zones and run additional learning experiments on each die while respecting the larger keep-out zones to compute additional design metrics. The dies can be binned into different Stock Keeping Units (SKUs) based on one or more of the computed design metrics. Circuit design tools automatically respect the keep-out regions for these dies to program them correctly in the field.
    Type: Application
    Filed: June 26, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Dheeraj Subbareddy, Ankireddy Nalamalpu, Mahesh A. Iyer
  • Publication number: 20190042702
    Abstract: The program directs a computer processor to implement a program that manages a device. The program stores a medication listing, together with medication consumption instructions. The program monitors one or more medication containers, which contain at least one medication for the patient. The program receives medication consumption data of the patient, including the name of the drug consumed, the quantity, and the time that the patient last consumed the one or more medications. The program receives patient condition data from one or more monitoring devices in real-time, which includes at least one measurement of a medical vital sign of the patient. Based on the patient condition data, the program recommends that the patient consume a dosage amount of a medication at a designated time, from the one or more medication containers, or locks the one or more medication containers to prevent an adverse drug reaction or overdose in the patient.
    Type: Application
    Filed: August 3, 2017
    Publication date: February 7, 2019
    Inventors: Varun Chandramouli, Anca Sailer, Sanjay Surendranath Girija, Mahesh Viswanathan
  • Publication number: 20190042445
    Abstract: Technologies for caching persistent two-level memory (2LM) data include a memory and a processor. The memory includes a volatile memory device and a non-volatile memory device. The processor determines a persistent memory address space for persistent 2LM data and determines one or more non-volatile memory devices that the persistent memory address space is mapped to. The processor further configures the persistent memory address space of the non-volatile memory device to operate in a persistent 2LM mode and further configures an operating system to cache accesses to persistent memory address space in volatile memory.
    Type: Application
    Filed: August 7, 2017
    Publication date: February 7, 2019
    Inventors: Muthukumar P. Swaminathan, Murugasamy K. Nachimuthu, Mahesh S. Natu
  • Publication number: 20190044702
    Abstract: Examples disclosed herein include are computing device hardware components, computing devices, systems, machine-readable mediums, and interconnect protocols that provide for code object measurement of a peripheral device and a method for accessing the measurements to verify integrity across a computing interconnect (e.g., Peripheral Component Interconnect Express—PCIe). For example, a cryptographic processor of a PCIe endpoint (such as a peripheral) may take a measurement (e.g., computing a hash value) of a code object on the device prior to executing the code object. This measurement may be placed in a register that is accessible to another component, such as a host operating system across a PCIe bus for interrogation. The host operating system may utilize an interconnect protocol, such as a PCIe protocol to access the measurement. These measurements may be consumed by a Trusted Platform Manager or other components of a host system that may verify the measurements.
    Type: Application
    Filed: December 8, 2017
    Publication date: February 7, 2019
    Inventors: Mahesh Natu, Adrian Pearson
  • Patent number: 10198845
    Abstract: Systems and methods for animating expressions of 3D models from captured images of a user's face in accordance with various embodiments of the invention are disclosed. In many embodiments, expressions are identified based on landmarks from images of a user's face. In certain embodiments, weights for morph targets of a 3D model are calculated based on identified landmarks and/or weights for predefined facial expressions to animate expressions for the 3D model.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: February 5, 2019
    Assignee: LoomAi, Inc.
    Inventors: Kiran Bhat, Mahesh Ramasubramanian, Michael Palleschi, Andrew A. Johnson, Ian Sachs
  • Patent number: 10200041
    Abstract: An analog multiplexer may be used for sampling an input voltage that is capable of having a higher voltage level than an upper supply voltage. The analog multiplexer includes a plurality of input switch circuits and a shorting switch circuit. The plurality of input switch circuits include n-type or p-type laterally diffused field effect transistors (NLDFETs or PLDFETs). At least one of the input switch circuits includes a level shifting switch circuit that is able to sample an input voltage that is greater than the upper supply voltage for the multiplexer. A shorting switch circuit, at an output of the multiplexer, includes a capacitively coupled gate drive circuit and is configured to short a first differential output to a second differential output after the input voltage is sampled.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: February 5, 2019
    Assignee: Analog Devices Global
    Inventors: Jeremy R. Gorbold, Christian Steffen Birk, Gerard Mora Puchalt, Colin Charles Price, Michael C. W. Coln, Mahesh Madhavan Kumbaranthodiyil
  • Publication number: 20190034264
    Abstract: An error handling device logs errors in a computing system including a plurality of devices connected to the error handling device. The error handling device provides groups of error registers. Each group of error registers is associated with a value of a plurality of values. Each of the devices that communicate errors to the error handling device are associated with one of the values. The error handling device receives error messages from the devices connected to the error handling device and for each received error message of the received error messages, determines a value of the plurality of values associated with the device transmitting the received error message, determines the group of error registers associated with the determined value, and log the received error message in the determined group of error registers.
    Type: Application
    Filed: December 18, 2017
    Publication date: January 31, 2019
    Inventors: Sivakumar RADHAKRISHNAN, Malay TRIVEDI, Jayasekhar THOLIYIL, Erik A. MCSHANE, Roger W. LIU, Mahesh S. NATU