Abstract: In the present application, there is provided a decoding apparatus for decoding low density parity check codes, including: a plurality of storage sections configured to store logarithmic likelihood ratios or logarithmic posteriori probability ratios for one codeword into addresses thereof which are independent of each other thereamong; and a readout section configured to simultaneously read out, from among the logarithmic likelihood ratios or logarithmic posteriori probability ratios for the one codeword stored in the storage sections, a plurality of ones of the logarithmic likelihood ratios or logarithmic posteriori probability ratios which correspond to non-zero value elements in a predetermined one row of the check matrix used in a coding process of the low density parity check codes.

Abstract: An encoding method encodes by using a quasi-cyclic code having a code length of n=m n0 and an information word length of k=m k0. The method includes the steps of: creating a systematic code with as many as (n0?k0) parity bits inserted therein in units of an information word k0; making all combinations of (n0?k0) parity bit positions that may occur in units of no bits; describing many of m×m cyclic matrices by rearranging the sequence of columns in a parity check matrix in the combinations; subjecting the parity check matrix to elementary transformation to create a unit matrix in which (n?k)×(n?k) matrices made up of the columns corresponding to the parity bit positions; regarding the transformed matrix as a first matrix and this matrix minus the unit matrix as a second matrix; and allocating (n?k) bit positions for the parity bits in such a manner that the number of non-zero elements included in the second matrix is minimized.

Abstract: An encoding method is disclosed for use with an encoding apparatus for carrying out variable-length conversion encoding involving a look-ahead operation of at least either one information word or one code word upon encoding. The encoding method includes the step of performing conversion encoding in such a manner as to permit decoding of encoded words in units of a code word.

Abstract: The present invention establishes a metric calculation method. A constant calculation circuit 31 calculates constants V/2?A, V/2+A, and A/2, which are required to calculate branch metrics by using an average voltage V/2, corresponding to a parameter R input from an asymmetrical register, which is input from an average voltage register, and output them to adders 33, 35, and 36, respectively. A multiplier 32 multiplies an equalized signal yk by a value P of 1 or ?1 input from a polarity register. A bit shifter 37 shifts by c bits A/2?yk, corresponding to the parameter R input from the asymmetrical register, which is input from the adder 36. That is, the bit shifter 37 multiplies A/2?yk by ?, and outputs it to adders 38 and 39. However, when the parameter R is 0, the bit shifter 37 outputs 0 to the adders 38 and 39. The present invention can be applied to a recording and reproduction apparatus.

Abstract: The present invention allows two different block codes to be encoded by one-type of encoding section. A first-point-fixed encoding section divides m-bit data into a first-half code and a second-half code, and encodes them into an n-bit provisional code with fixed start-point state. A code A/B counter receives a reset-signal and outputs a code selection signal to a code-order reversing section and a top-code correction section. The code-order reversing section receives a codeword excluding the top code from the start-point-fixed encoding section; and outputs the codeword as is, when the code selection signal indicates a code B, and reverses the order of the codeword to generate a new codeword, and outputs the new codeword to a latch, when the code selection signal indicates a code A. The top-code correction section determines whether the top code needs to be modified, and modifies the top code, if necessary.

Abstract: A dielectric barrier discharge lamp drive circuit having a thickness so that sufficient mechanical strength of a glass plate is obtained and a relatively large illumination area. The drive circuit is driven at low voltage and reduces apparent current. The drive circuit applies a high frequency power to a flat panel discharge lamp (19) with a reactor (32). In a lighted state, a state close to a series resonance of the inductance of the reactor and an electrostatic capacity of the glass plate (11, 12) is set. The inductance value of the reactor is selected so that the frequency of the high frequency power is slightly smaller than the series resonance frequency, and the impedance of the load as viewed from an AC source (31) is set to the rated impedance. A high light emitting efficiency is obtained in such a configuration when Xe (xenon) gas that does not cause environmental problems is used as the discharge gas.

Abstract: In an encoding method to a self-orthogonal QC code whose parity check matrix is expressed by at least one circulant matrix, a code sequence is generated which satisfies a check matrix. The check matrix is designed so that a column weight w of each circulant matrix is three or larger and a minimum hamming distance of the code is w+2 or larger.

Abstract: A code sequence is encoded using a code conversion table in which the parity of the code sequence varies until the code states become equal to each other. The code word assignment used in this code conversion table is such that the decoded code word constraint length is 3 blocks and q0?q1 for an arbitrary information sequence is satisfied even if a DC control bit is inserted at any of the first and second bits of an information word. Code states s0 and s1 when information sequences d0 and d1 resulted from insertion of provisional DC control bits 1 and 0 inserted at the top of an information sequence “1, 1, 0, 0, 0, 1, 0” are encoded starting with a state 3 according to a predetermined code conversion table are equal to each other, namely, s0=s1=6, in a third block, and two's complement q0 of a sum of code sequences c0 up to a time when the code states are equal to each other is “0,” while two's complement q1 of a sum of code sequences c1 up to that time is “1”. That is, the condition that q0?q1 is met.

Abstract: A code sequence is encoded using a code conversion table in which the parity of the code sequence varies until the code states become equal to each other. The code word assignment used in this code conversion table is such that the decoded code word constraint length is 3 blocks and q0?q1 for an arbitrary information sequence is satisfied even if a DC control bit is inserted at any of the first and second bits of an information word. Code states s0 and s1 when information sequences d0 and d1 resulted from insertion of provisional DC control bits 1 and 0 inserted at the top of an information sequence “1, 1, 0, 0, 0, 1, 0” are encoded starting with a state 3 according to a predetermined code conversion table are equal to each other, namely, s0=s1=6, in a third block, and two's complement q0 of a sum of code sequences c0 up to a time when the code states are equal to each other is “0,” while two's complement q1 of a sum of code sequences c1 up to that time is “1”. That is, the condition that q0?q1 is met.

Abstract: A code sequence is encoded using a code conversion table in which the parity of the code sequence varies until the code states become equal to each other. The code word assignment used in this code conversion table is such that the decoded code word constraint length is 3 blocks and q0?q1 for an arbitrary information sequence is satisfied even if a DC control bit is inserted at any of the first and second bits of an information word. Code states s0 and s1 when information sequences d0 and d1 resulted from insertion of provisional DC control bits 1 and 0 inserted at the top of an information sequence “1, 1, 0, 0, 0, 1, 0” are encoded starting with a state 3 according to a predetermined code conversion table are equal to each other, namely, s0=s1=6, in a third block, and two's complement q0 of a sum of code sequences c0 up to a time when the code states are equal to each other is “0,” while two's complement q1 of a sum of code sequences c1 up to that time is “1”. That is, the condition that q0?q1 is met.

Abstract: A field effect transistor comprises, at least, a channel forming region formed in a semiconductor layer, and a gate electrode provided in face-to-face relation with the channel forming region via a gate insulating film, wherein the semiconductor layer is made of a mixture of a semiconductor material layer and conductive particles. The field effect transistor is capable of enhancing a carrier mobility.

Abstract: The present invention is to reduce the maximum magnetization reversal interval of a trellis code. A trellis diagram for the trellis code takes into consideration a constraint condition on the DSV of a code and an inter-symbol-interference for three bits. The minimum squared Euclidean distance is 4. When a non-interleaving encoder and a non-de-interleaving code detector are constructed using the trellis diagram, the maximum magnetization reversal interval of a trellis code to be used is reduced to half of that in a known case while having the error rate and circuit size approximately equal to those in the known case. The trellis diagram has a basic repeating unit for two bits. In the actual apparatus, the trellis diagram is repeatedly used. The present invention is applicable to a read/write apparatus.

Abstract: A code sequence is encoded using a code conversion table in which the parity of the code sequence varies until the code states become equal to each other. The code word assignment used in this code conversion table is such that the decoded code word constraint length is 3 blocks and q0?q1 for an arbitrary information sequence is satisfied even if a DC control bit is inserted at any of the first and second bits of an information word. Code states s0 and s1 when information sequences d0 and d1 resulted from insertion of provisional DC control bits 1 and 0 inserted at the top of an information sequence “1, 1, 0, 0, 0, 1, 0” are encoded starting with a state 3 according to a predetermined code conversion table are equal to each other, namely, s0=s1=6, in a third block, and two's complement q0 of a sum of code sequences c0 up to a time when the code states are equal to each other is “0,” while two's complement q1 of a sum of code sequences c1 up to that time is “1”. That is, the condition that q0?q1 is met.

Abstract: The present invention provides a data processing method that can reduce the number of data blocks belonging to a same error-correcting code word for two-dimensional error bursts that give rise to errors over a plurality of transmission channels.

Abstract: A code sequence is encoded using a code conversion table in which the parity of the code sequence varies until the code states become equal to each other. The code word assignment used in this code conversion table is such that the decoded code word constraint length is 3 blocks and q0?q1 for an arbitrary information sequence is satisfied even if a DC control bit is inserted at any of the first and second bits of an information word. For example, code states s0 and s1 when information sequences d0 and d1 resulted from insertion of provisional DC control bits 1 and 0 inserted at the top of an information sequence “1, 1, 0, 0, 0, 1, 0” are encoded starting with a state 3 according to a predetermined code conversion table are equal to each other, namely, s0=s1=6, in a third block, and two's complement q0 of a sum of code sequences c0 up to a time when the code states are equal to each other is “0” while two's complement q1 of a sum of code sequences c1 up to that time is “1”.

Abstract: A code sequence is encoded using a code conversion table in which the parity of the code sequence varies until the code states become equal to each other. The code word assignment used in this code conversion table is such that the decoded code word constraint length is 3 blocks and q0?q1 for an arbitrary information sequence is satisfied even if a DC control bit is inserted at any of the first and second bits of an information word. For example, code states s0 and s1 when information sequences d0 and d1 resulted from insertion of provisional DC control bits 1 and 0 inserted at the top of an information sequence “1, 1, 0, 0, 0, 1, 0” are encoded starting with a state 3 according to a predetermined code conversion table are equal to each other, namely, s0=s1=6, in a third block, and two's complement q0 of a sum of code sequences c0 up to a time when the code states are equal to each other is “0” while two's complement q1 of a sum of code sequences c1 up to that time is “1”.

Abstract: A code sequence is encoded using a code conversion table in which the parity of the code sequence varies until the code states become equal to each other. The code word assignment used in this code conversion table is such that the decoded code word constraint length is 3 blocks and q0?q1 for an arbitrary information sequence is satisfied even if a DC control bit is inserted at any of the first and second bits of an information word. For example, code states s0 and s1 when information sequences d0 and d1 resulted from insertion of provisional DC control bits 1 and 0 inserted at the top of an information sequence “1, 1, 0, 0, 0, 1, 0” are encoded starting with a state 3 according to a predetermined code conversion table are equal to each other, namely, s0=s1=6, in a third block, and two's complement q0 of a sum of code sequences c0 up to a time when the code states are equal to each other is “0” while two's complement q1 of a sum of code sequences c1 up to that time is “1”.

Abstract: A code sequence is encoded using a code conversion table in which the parity of the code sequence varies until the code states become equal to each other. The code word assignment used in this code conversion table is such that the decoded code word constraint length is 3 blocks and q0?q1 for an arbitrary information sequence is satisfied even if a DC control bit is inserted at any of the first and second bits of an information word. For example, code states s0 and s1 when information sequences d0 and d1 resulted from insertion of provisional DC control bits 1 and 0 inserted at the top of an information sequence “1, 1, 0, 0, 0, 1, 0” are encoded starting with a state 3 according to a predetermined code conversion table are equal to each other, namely, s0=s1=6, in a third block, and two's complement q0 of a sum of code sequences c0 up to a time when the code states are equal to each other is “0” while two's complement q1 of a sum of code sequences c1 up to that time is “1”.

Abstract: The present invention allows two different block codes to be encoded by a substantially one-type encoding section. A first-point-fixed encoding section 21 divides m-bit data into a first-half code and a second-half code, and encodes them to convert to an n-bit provisional code with the start-point state of the code being fixed. A code A/B counter 24 receives a reset-signal input and outputs a code selection signal to a code-order reversing section 22 and a top-code correction section 23. The code-order reversing section 22 receives a codeword except for the top code from the start-point-fixed encoding section 21; and outputs the codeword as is, which does not include the top code, when the code selection signal indicates a code B, and reverses the order of the codeword to generate a codeword, which does not include the top code, and outputs it when the code selection signal indicates a code A, to a latch 25.

Abstract: A code sequence is encoded using a code conversion table in which the parity of the code sequence varies until the code states become equal to each other. The code word assignment used in this code conversion table is such that the decoded code word constraint length is 3 blocks and q0?q1 for an arbitrary information sequence is satisfied even if a DC control bit is inserted at any of the first and second bits of an information word. For example, code states s0 and s1 when information sequences d0 and d1 resulted from insertion of provisional DC control bits 1 and 0 inserted at the top of an information sequence “1, 1, 0, 0, 0, 1, 0” are encoded starting with a state 3 according to a predetermined code conversion table are equal to each other, namely, s0=s1=6, in a third block, and two's complement q0 of a sum of code sequences c0 up to a time when the code states are equal to each other is “0” while two's complement q1 of a sum of code sequences c1 up to that time is “1”.