Abstract: A semiconductor integrated circuit device of a standard cell system of this invention includes a cell array constituted by linearly arranging a plurality of cells each having a predetermined unit logical function. A Vcc power supply line and a GND power supply line are formed of a first aluminum layer, to supply a power supply voltage to the cells in the cell arrays. Power supply buses formed of a second aluminum layer are arranged on both the ends of the Vcc power supply line and the GND power supply line through a via hole, in a direction perpendicular to the Vcc power supply line and the GND power supply line. A Vcc power supply line and a GND power supply line formed of a third aluminum layer are arranged on the Vcc power supply line and the GND power supply line, at a central portion of the cell array, through a via hole, and extend in the same direction as the Vcc power supply lines and the GND power supply line, both mode of the first aluminum layer.

Abstract: A directly-heated cathode structure for use in a compact cathode ray tube comprises an insulating support body, a pair of cathode lead pins fixedly carried in the insulating support body, and a filament extending between the leading ends of said cathode lead pins. An electron emitting material is applied to and coated on the filament over its entire length including its two ends joining with the leading ends of the cathode lead pins so that the electron emitting material once hardened ensures that the two ends of the filament are firmly fixed to the leading ends of the cathode lead pins. The insulating support body may have a groove which is formed across the upper face thereof and within which the leading ends of the cathode lead pins are exposed in a spaced relation, which helps confining undesirable scattering of the electron emitting material when sprayed to the filament.

Abstract: An NOx sensor for determining the concentration of NOx contained in a measurement gas, having first and second electrochemical detecting elements each of which includes an oxygen pumping cell and an oxygen sensing cell. Each of the pumping and sensing cells of the first and second detecting elements consists of a solid electrolyte and a pair of electrodes. At least one of the electrodes of the oxygen pumping and sensing cells of the second detecting elements which are exposed to the introduced measurement gas, is used as a catalytic electrode which is provided with a catalyst for reducing the nitrogen oxides contained in the measurement gas. The second detecting element detects an oxygen partial pressure of the measurement gas while the nitrogen oxides are reduced by the catalyst of the catalytic electrode.

Abstract: The basic cells of a parallel multiplier are arranged into arrays corresponding in number to the number of bits of multiplier data Y and multiplicand data X. Multiplicand data supply lines supply bit data Xi corresponding to the basic cell of the multiplicand data X, its inverted data Xi, bit data Xi-1 one digit lower than said corresponding bit, and its inverted data Xi-1 to each of the basic cells. Decoders decode multiplier data Y based on the Booth's algorithm. These decoders supply a prescribed select signal to the basic cells. The basic cells comprise a selecting circuit for selectively inputting one of data Xi, Xi, Xi-1, Xi-1 and "0" according to the select signal from the decoders, and a full adder. The full adder receives the data input by the selecting circuit as the augend data and receives the addend and carry data from the previous row of basic cells. The full adder adds the augend, addend and carry data, and outputs sum and carry data.

Abstract: A microcomputer which is set to a power-save mode by an external signal or an output signal from an instruction decoder, and is provided with a flip-flop circuit which is set when microcomputer is set to a power-save mode and is reset upon receipt of an external interruption signal or reset signal, and sends forth a power-save output signal.

Abstract: A static memory device includes memory cells arranged in the form of a matrix. The memory cells are each formed of a flip-flop circuit and first and second MOS transistors whose current paths are each coupled between a corresponding one of first and second bistable output nodes of the flip-flop circuit and a corresponding one of paired digit lines and whose gates are coupled to first and second word lines, respectively.