Abstract: A method includes, in a data storage device, receiving a read command to read a portion of a wordline of a memory. The method also includes determining a first and a last storage element of the wordline to identify a set of storage elements. The method includes determining a first set and a second set of sense amplifiers of multiple sense amplifiers coupled to the wordline. The first set of sense amplifiers is coupled to the set of storage elements and the second set of sense amplifiers is coupled to one or more storage elements of the wordline other than the first set of storage elements. The method includes reading data by applying a read voltage to the wordline and providing a sense enable signal to each sense amplifier of the first set of sense amplifiers while each sense amplifier of the second set of sense amplifiers is disabled.

Abstract: A storage device includes a controller and a non-volatile memory that includes a three-dimensional (3D) memory. A method performed in the data storage device includes receiving, at the controller, first data to be stored at the non-volatile memory. The method further includes sending, from the controller, the first data, first dummy data, and second dummy data to the non-volatile memory to be stored at respective logical pages of a single physical page in the non-volatile memory. The single physical page includes multiple storage elements that are programmable into multiple voltage states according to a mapping of bits to states. The first dummy data and the second dummy data prevent a storage element of the single physical page from being programmed to a particular voltage state of the multiple voltage states.

Abstract: A storage device includes non-volatile memory and a controller. A method performed in the data storage device includes receiving, at the controller, first data and second data to be stored at the non-volatile memory. The method further includes sending, from the controller, the first data, the second data, and dummy data to the non-volatile memory to be stored at respective logical pages of a single physical page in the non-volatile memory. The single physical page includes multiple storage elements that are programmable into multiple voltage states according to a mapping of bits to states. The dummy data prevents a storage element of the single physical page from being programmed to a particular voltage state of the multiple voltage states.

Abstract: A storage device includes a controller and a non-volatile memory that includes a three-dimensional (3D) memory. A method performed in the data storage device includes receiving, at the controller, first data and second data to be stored at the non-volatile memory. The method further includes sending, from the controller, the first data, the second data, and dummy data to the non-volatile memory to be stored at respective logical pages of a single physical page in the non-volatile memory. The single physical page includes multiple storage elements that are programmable into multiple voltage states according to a mapping of bits to states. The dummy data prevents a storage element of the single physical page from being programmed to a particular voltage state of the multiple voltage states.

Abstract: A storage device includes non-volatile memory and a controller. A method performed in the data storage device includes receiving, at the controller, first data to be stored at the non-volatile memory. The method further includes sending, from the controller, the first data, first dummy data, and second dummy data to the non-volatile memory to be stored at respective logical pages of a single physical page in the non-volatile memory. The single physical page includes multiple storage elements that are programmable into multiple voltage states according to a mapping of bits to states. The first dummy data and the second dummy data prevent a storage element of the single physical page from being programmed to a particular voltage state of the multiple voltage states.

Abstract: A data storage device includes a memory die including a plurality of storage elements arranged in a three dimensional (3D) memory configuration and a controller die coupled to the memory die via a bus including a plurality of electrical contacts between adjacent surfaces of the memory die and the controller die. A method performed at the data storage device includes receiving, at the controller die, data to be stored at the memory die and generating a codeword representing the data. The codeword includes a particular number of bits. The method also includes sending signals from the controller die to the memory die via the plurality of electrical contacts. The plurality of electrical contacts includes at least as many electrical contacts as the particular number of bits of the codeword, and the signals representing the codeword are sent from the controller die to the memory die in parallel.

Abstract: In a data storage device that includes a non-volatile memory, a method includes determining that a current error correction code page count (CEC) is at least as large as a target error correction code page count (TEC). The CEC is a page count of error correction code (ECC) pages of data read from the memory during a time period from a previous time to a particular time using a set of reference voltages. In response to the CEC being at least as large as the TEC, the method includes updating a subset of the set of reference voltages conditioned upon a difference between a current mean error count (CMEC) and a previous mean error count being at least as large as a target mean delta error. The CMEC is based on a count of read errors associated with the ECC pages read during the time period.

Abstract: A method may be performed at a data storage device that includes a memory and a controller. The method includes providing user data to a variable-bit error correction coding (ECC) encoder. The ECC encoder generates a first set of parity bits. A first number of parity bits in the first set of parity bits is determined based on stored counts of read errors. The method also includes storing the user data and the first set of parity bits to a memory of the data storage device.

Abstract: A data storage device includes a memory and a controller and may perform a method that includes updating, in a controller of the data storage device, a value of a particular write/erase (W/E) counter of a set of counters in response to an erase operation to a particular region of the non-volatile memory that is tracked by the particular W/E counter and that includes a storage element that is tracked by a particular cell erase counter of the set of counters. The method includes, in response to the value of the particular W/E counter indicating that a count of erase operations to the particular region satisfies a first threshold, initiating a remedial action to the particular region of the non-volatile memory at least partially based on the value of the particular cell erase counter.

Abstract: A data storage device includes a memory and a controller and may perform a method that includes updating, in the controller, a value of a particular counter of a set of counters in response to an erase operation to a particular region of the non-volatile memory that is tracked by the particular counter. The method includes, in response to the value of the particular counter indicating that a count of erase operations to the particular region satisfies a first threshold, initiating a remedial action to the particular region of the non-volatile memory.

Abstract: A data storage device includes a memory and a controller and may perform a method that includes comparing, in the controller, a count of erase pulses to an erase pulse threshold. The count of erase pulses corresponds to a particular region of the non-volatile memory. The method includes, in response to the count of erase pulse satisfying the erase pulse threshold, initiating a remedial action with respect to the particular region of the non-volatile memory.

Abstract: A method includes decreasing a programming step size from a first value to a second value for a block of a memory device. The programming step size is decreased at least partially based on determining that an error count corresponding to the block satisfies a threshold.

Abstract: A method includes, in a data storage device that includes a non-volatile memory, selecting an updated reference voltage as one of a reference voltage, a first alternate reference voltage and a second alternate reference voltage. The first alternate reference voltage and the second alternate reference voltage are calculated based on the reference voltage and based on a voltage increment. Selection of the updated reference voltage is based on a comparison of error counts, each error count associated with a unique one of the reference voltage, the first alternate reference voltage, and the second alternate reference voltage. The method includes resetting the reference voltage to the updated reference voltage, resetting the voltage increment to a reset voltage increment that is smaller than the voltage increment, and selecting an additional updated reference voltage based on the reset reference voltage and based on the reset voltage increment.

Abstract: A data storage device includes non-volatile memory and a controller. The controller is configured to read first data from the non-volatile memory. The first data indicates a first count of storage elements of the group that have a first activation status when sensed with a first reference voltage at a first time. The controller is configured to read second data from the non-volatile memory. The second data indicates a second count of storage elements of the group that have the first activation status when sensed with the first reference voltage at a second time. The controller is configured to generate an updated first reference voltage at least partially based on a difference between the first count and the second count and based on one or more parameters corresponding to a distribution of threshold voltages of storage elements at the first time.

Abstract: A method in a data storage device including a memory and an error correction coding (ECC) engine. A first ECC page including a data block and first main ECC data is stored to the memory. The first main ECC data is usable by the ECC engine to correct errors in the first ECC page. A second ECC page including first additional ECC data is also stored to the memory. The first additional ECC data is usable by the ECC engine to correct errors in a single sub-block of multiple sub-blocks within the data block.

Abstract: An apparatus includes a semiconductor device that includes a multi-ported three-dimensional (3D) memory. The multi-ported 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The multi-ported 3D memory includes circuitry associated with operation of the multiple memory cells.

Abstract: An apparatus includes a first semiconductor device including a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory further includes circuitry associated with operation of the multiple memory cells. The apparatus includes a second semiconductor device coupled to the first semiconductor device. The second semiconductor device includes a charge pump, and the 3D memory does not include a charge pump.

Abstract: An apparatus includes a semiconductor device that includes a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory includes circuitry associated with operation of the multiple memory cells and includes a serializer/deserializer interface.

Abstract: An apparatus includes a semiconductor device including a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory includes circuitry associated with operation of the multiple memory cells and includes a differential signaling interface.

Abstract: A data storage device includes non-volatile memory and a controller. The controller is configured to, at a first time, determine a first count of storage elements having threshold voltages within a voltage range that corresponds to a first reference voltage. The controller is further configured to, at a second time, determine a second count of storage elements having threshold voltages within the voltage range. The controller is further configured to calculate an updated first reference voltage at least partially based on the first reference voltage, the first count, and the second count.