Abstract: A semiconductor device according to an embodiment includes a first gate-all-around (GAA) transistor and a second GAA transistor. The first GAA transistor includes a first plurality of channel members, a first interfacial layer over the first plurality of channel members, a first hafnium-containing dielectric layer over the first interfacial layer, and a metal gate electrode layer over the first hafnium-containing dielectric layer. The second GAA transistor includes a second plurality of channel members, a second interfacial layer over the second plurality of channel members, a second hafnium-containing dielectric layer over the second interfacial layer, and the metal gate electrode layer over the second hafnium-containing dielectric layer. A first thickness of the first interfacial layer is greater than a second thickness of the second interfacial layer. A third thickness of the first hafnium-containing dielectric layer is smaller than a fourth thickness of the second hafnium-containing dielectric layer.

Abstract: A method includes providing semiconductor channel layers over a substrate; forming a first dipole layer wrapping around the semiconductor channel layers; forming an interfacial dielectric layer wrapping around the first dipole layer; forming a high-k dielectric layer wrapping around the interfacial dielectric layer; forming a second dipole layer wrapping around the high-k dielectric layer; performing a thermal process to drive at least some dipole elements from the second dipole layer into the high-k dielectric layer; removing the second dipole layer; and forming a work function metal layer wrapping around the high-k dielectric layer.

Abstract: A method includes providing a structure having a substrate and a stack of semiconductor layers over a surface of the substrate and spaced vertically one from another; forming an interfacial layer wrapping around each of the semiconductor layers; forming a high-k dielectric layer over the interfacial layer and wrapping around each of the semiconductor layers; and forming a capping layer over the high-k dielectric layer and wrapping around each of the semiconductor layers. With the capping layer wrapping around each of the semiconductor layers, the method further includes performing a thermal treatment to the structure, thereby increasing a thickness of the interfacial layer. After the performing of the thermal treatment, the method further includes removing the capping layer.

Abstract: A method of integrated circuit (IC) fabrication includes exposing a plurality of channel regions including a p-type channel region and an n-type channel region; forming a gate dielectric layer over the exposed channel regions; and forming a work function metal (WFM) structure over the gate dielectric layer. The WFM structure includes a p-type WFM portion formed over the p-type channel region and an n-type WFM portion formed over the n-type channel region, and the p-type WFM portion is thinner than the n-type WFM portion. The method further includes forming a fill metal layer over the WFM structure such that the fill metal layer is in direct contact with both the p-type and n-type WFM portions.

Abstract: In some embodiments, the present disclosure relates to an integrated chip including first, second, and third nanosheet field effect transistors (NSFETs) arranged over a substrate. The first NSFET has a first threshold voltage and includes first nanosheet channel structures embedded in a first gate electrode layer. The first nanosheet channel structures extend from a first source/drain region to a second source/drain region. The second NSFET has a second threshold voltage different than the first threshold voltage and includes second nanosheet channel structures embedded in a second gate electrode layer. The second nanosheet channel structures extend from a third source/drain region to a fourth source/drain region. The third NSFET has a third threshold voltage different than the second threshold voltage and includes third nanosheet channel structures embedded in a third gate electrode layer. The third nanosheet channel structures extend from a fifth source/drain region to a sixth source/drain region.

Abstract: In a method of manufacturing a semiconductor device, a support layer is formed over a substrate. A patterned semiconductor layer made of a first semiconductor material is formed over the support layer. A part of the support layer under a part of the semiconductor layer is removed, thereby forming a semiconductor wire. A semiconductor shell layer made of a second semiconductor material different from the first semiconductor material is formed around the semiconductor wire.

Abstract: A method of fabricating semiconductor devices includes forming a plurality of first and second semiconductor nanosheets in p-type and n-type device regions, respectively. An n-type work function layer is deposited to surround each of the first and second semiconductor nanosheets. A passivation layer is deposited on the n-type work function layer to surround each of the first and second semiconductor nanosheets. A patterned mask is formed on the passivation layer in the n-type device region, and the n-type work function layer and the passivation layer in the p-type device region are removed in an etching process using the patterned mask as an etching mask. Then, the patterned mask is removed, and a p-type work function layer is deposited to surround the first semiconductor nanosheets and to cover the passivation layer.

Abstract: A semiconductor having a first gate-all-around (GAA) transistor, a second GAA transistor, and a third GAA transistor is provided. The first (GAA) transistor includes a first plurality of channel members, a gate dielectric layer over the first plurality of channel members, a first work function layer over the gate dielectric layer, and a glue layer over the first work function layer. The second GAA transistor include a second plurality of channel members, the gate dielectric layer over the second plurality of channel members, and a second work function layer over the gate dielectric layer, the first work function layer over and in contact with the second work function layer, and the glue layer over the first work function layer. The third GAA transistor includes a third plurality of channel members, the gate dielectric layer over the third plurality of channel members, and the glue layer over the gate dielectric layer.

Abstract: A replication list table structure for multicast packet replication is provided. The replication list table structure includes a plurality of entries. Each one of the plurality of entries includes a first field, a second field, a third field and a fourth field. For each one of the plurality of entries, the first field is used to declare whether the entry is an end of a program execution, the second field is used to declare the fourth field as a first type field for indicating a switch how to modify a header of a multicast packet, or as a second type field for indicating the switch, while reading the list, to jump to another one of the plurality entries, and the third field is preset to the first type field for indicating the switch how to modify the header of the multicast packet.

Abstract: A semiconductor device according to an embodiment includes a first gate-all-around (GAA) transistor and a second GAA transistor. The first GAA transistor includes a first plurality of channel members, a first interfacial layer over the first plurality of channel members, a first hafnium-containing dielectric layer over the first interfacial layer, and a metal gate electrode layer over the first hafnium-containing dielectric layer. The second GAA transistor includes a second plurality of channel members, a second interfacial layer over the second plurality of channel members, a second hafnium-containing dielectric layer over the second interfacial layer, and the metal gate electrode layer over the second hafnium-containing dielectric layer. A first thickness of the first interfacial layer is greater than a second thickness of the second interfacial layer. A third thickness of the first hafnium-containing dielectric layer is smaller than a fourth thickness of the second hafnium-containing dielectric layer.

Abstract: A method of fabricating an integrated circuit (IC) structure, includes forming a gate trench that exposes a portion of each of a plurality of fins and forming a threshold voltage (Vt) tuning dielectric layer in the gate trench over the plurality of fins. Properties of the Vt tuning dielectric layer are adjusted during the forming to achieve a different Vt for each of the plurality of fins. The method also includes forming a glue metal layer over the Vt tuning dielectric layer; and forming a fill metal layer over the glue metal layer. The fill metal layer has a substantially uniform thickness over top surfaces of the plurality of fins.

Abstract: A semiconductor device according to the present disclosure includes a source feature and a drain feature, a plurality of semiconductor nanostructures extending between the source feature and the drain feature, a gate structure wrapping around each of the plurality of semiconductor nanostructures, a bottom dielectric layer over the gate structure and the drain feature, a backside power rail disposed over the bottom dielectric layer, and a backside source contact disposed between the source feature and the backside power rail. The backside source contact extends through the bottom dielectric layer.

Abstract: A method includes providing a structure having a substrate, first and second channel layers over the substrate, and first and second gate dielectric layers over the first and the second channel layers respectively. The method further includes forming a first dipole pattern over the first gate dielectric layer, the first dipole pattern having a first dipole material that is of a first conductivity type; forming a second dipole pattern over the second gate dielectric layer, the second dipole pattern having a second dipole material that is of a second conductivity type opposite to the first conductivity type; and annealing the structure such that elements of the first dipole pattern are driven into the first gate dielectric layer and elements of the second dipole pattern are driven into the second gate dielectric layer.

Abstract: A semiconductor device according to the present disclosure includes a fin structure over a substrate, a vertical stack of silicon nanostructures disposed over the fin structure, an isolation structure disposed around the fin structure, a germanium-containing interfacial layer wrapping around each of the vertical stack of silicon nanostructures, a gate dielectric layer wrapping around the germanium-containing interfacial layer, and a gate electrode layer wrapping around the gate dielectric layer.

Abstract: A semiconductor device includes a first interconnect structure; multiple channel layers stacked over the first interconnect structure; a gate stack wrapping around each of the channel layers except a bottommost one of the channel layers; a source/drain feature adjoining the channel layers; a first conductive via connecting the first interconnect structure to a bottom of the source/drain feature; and a dielectric feature between the bottommost one of the channel layers and the first conductive via.

Abstract: A method includes providing first and second channel layers in a p-type region and an n-type region respectively, forming a gate dielectric layer around the first and second channel layers, and forming a sacrificial layer around the gate dielectric layer. The sacrificial layer merges in space between the first channel layers and between the second channel layers. The method further includes etching the sacrificial layer such that only portions of the sacrificial layer in the space between the first channel layers and between the second channel layers remain, forming a mask covering the p-type region and exposing the n-type region, removing the sacrificial layer from the n-type region, removing the mask, and forming an n-type work function metal layer around the gate dielectric layer in the n-type region and over the gate dielectric layer and the sacrificial layer in the p-type region.

Abstract: A semiconductor having a first gate-all-around (GAA) transistor, a second GAA transistor, and a third GAA transistor is provided. The first (GAA) transistor includes a first plurality of channel members, a gate dielectric layer over the first plurality of channel members, a first work function layer over the gate dielectric layer, and a glue layer over the first work function layer. The second GAA transistor include a second plurality of channel members, the gate dielectric layer over the second plurality of channel members, and a second work function layer over the gate dielectric layer, the first work function layer over and in contact with the second work function layer, and the glue layer over the first work function layer. The third GAA transistor includes a third plurality of channel members, the gate dielectric layer over the third plurality of channel members, and the glue layer over the gate dielectric layer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises semiconductor layers over a substrate, wherein the semiconductor layers are separated from each other and are stacked up along a direction substantially perpendicular to a top surface of the substrate; a gate structure wrapping each of the semiconductor layers; a spacer structure wrapping an edge portion of each of the semiconductor layers; and a dummy fin structure contacting a sidewall of the gate structure, wherein the dummy fin structure is separated from a sidewall of the spacer structure by a dielectric liner.

Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a gate dielectric layer around first channel layers in a p-type gate region and around second channel layers in an n-type gate region. Sacrificial features are formed between the second channel layers in the n-type gate region. A p-type work function layer is formed over the gate dielectric layer in the p-type gate region and the n-type gate region. After removing the p-type work function layer from the n-type gate region, the sacrificial features are removed from between the second channel layers in the n-type gate region. An n-type work function layer is formed over the gate dielectric layer in the n-type gate region. A metal fill layer is formed over the p-type work function layer in the p-type gate region and the n-type work function layer in the n-type gate region.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor layers and second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers are separated and stacked up, and a thickness of each second semiconductor layer is less than a thickness of each first semiconductor layer; a first interfacial layer around each first semiconductor layer; a second interfacial layer around each second semiconductor layer; a first dipole gate dielectric layer around each first semiconductor layer and over the first interfacial layer; a second dipole gate dielectric layer around each second semiconductor layer and over the second interfacial layer; a first gate electrode around each first semiconductor layer and over the first dipole gate dielectric layer; and a second gate electrode around each second semiconductor layer and over the second dipole gate dielectric layer.