Patents by Inventor Mao-Lin Huang
Mao-Lin Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9263295Abstract: A nanowire field effect transistor (FET) device and method for forming the same is disclosed. The device comprises: a semiconductor substrate; a device layer including a source region and a drain region connected by a suspended nanowire channel; and etch stop layers respectively arranged beneath the source region and the drain region, the etch stop layers forming support structures interposed between the semiconductor substrate and the source and drain regions. The suspended nanowire channel is formed by etching a sacrificial material disposed beneath the suspended nanowire channel and between the etch stop layers. The etching is selective to the sacrificial material to prevent the removal of the etch stop layers beneath the source region and the drain region.Type: GrantFiled: May 26, 2015Date of Patent: February 16, 2016Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chien-Hsun Wang, Mao-Lin Huang, Chun-Hsiung Lin, Jean-Pierre Colinge
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Publication number: 20160013054Abstract: A method for forming a semiconductor device having a fin-type channel is provided. The method may include the following operations: forming a first buffer layer over a substrate; forming a first dielectric layer over the first buffer layer; patterning the first dielectric layer over the first buffer layer; forming a barrier layer over the first buffer layer; forming a second dielectric layer over the barrier layer; patterning the second dielectric layer over the barrier layer; forming a channel layer over the barrier layer; and patterning the second dielectric layer, such that at least a portion of the channel layer protrudes to form the fin-type channel.Type: ApplicationFiled: September 23, 2015Publication date: January 14, 2016Inventors: CHIEN-HSUN WANG, CHUN-HSIUNG LIN, MAO-LIN HUANG
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Patent number: 9214513Abstract: According to an exemplary embodiment, a method of forming a fin structure is provided. The method includes the following operations: etching a first dielectric layer to form at least one recess and a first core portion of a fin core; form an oxide layer as a shallow trench isolation layer in the recess; etching back the oxide layer to expose a portion of the fin core; and forming a fin shell to cover a sidewall of the exposed portion of the fin core.Type: GrantFiled: February 13, 2014Date of Patent: December 15, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chun-Hsiung Lin, Carlos H. Diaz, Hui-Cheng Chang, Syun-Ming Jang, Mao-Lin Huang, Chien-Hsun Wang
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Patent number: 9184289Abstract: A semiconductor devices and method of formation are provided herein. A semiconductor device includes a gate structure over a channel and an active region adjacent the channel. The active region includes a repaired doped region and a growth region over the repaired doped region. The repaired doped region includes a first dopant and a second dopant, where the second dopant is from the growth region. A method of forming a semiconductor device includes increasing a temperature during exposure to at least one of dopant(s) or agent(s) to form an active region adjacent a channel, where the active region includes a repaired doped region and a growth region over the repaired doped region.Type: GrantFiled: November 8, 2013Date of Patent: November 10, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Mao-Lin Huang, Chien-Hsun Wang, Chun-Hsiung Lin, Meng-Ku Chen, Li-Ting Wang, Hung-Ta Lin
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Patent number: 9166035Abstract: A transistor includes a gate terminal, a source terminal and a drain terminal. At least one of the source and drain terminals has a layered configuration that includes a terminal layer and an intervening layer. The terminal layer has a top surface and a bottom surface. The intervening layer is located within the terminal layer, between and spaced from the top and bottom surfaces, is oriented to be perpendicular to current flow, and is less than one tenth the thickness of the terminal layer. The terminal layer and the intervening layer include a common semiconductive compound and a common dopant, with a concentration of the dopant in the intervening layer being over ten times an average concentration of the dopant in the terminal layer.Type: GrantFiled: September 12, 2013Date of Patent: October 20, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hung-Ta Lin, Mao-Lin Huang, Li-Ting Wang, Chien-Hsun Wang, Meng-Ku Chen, Chun-Hsiung Lin, Pang-Yen Tsai, Hui-Cheng Chang
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Patent number: 9147766Abstract: A method for forming a semiconductor device having a fin-type channel is provided. The method may include the following operations: forming a first buffer layer over a substrate; forming a first dielectric layer over the first buffer layer; patterning the first dielectric layer over the first buffer layer; forming a barrier layer over the first buffer layer; forming a second dielectric layer over the barrier layer; patterning the second dielectric layer over the barrier layer; forming a channel layer over the barrier layer; and patterning the second dielectric layer, such that at least a portion of the channel layer protrudes to form the fin-type channel.Type: GrantFiled: November 14, 2013Date of Patent: September 29, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chien-Hsun Wang, Chun-Hsiung Lin, Mao-Lin Huang
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Publication number: 20150263094Abstract: A device structure includes: a core structure formed on a support, and a shell material formed on the core structure and surrounding at least part of the core structure. The shell material and the core structure are configured to form a quantum-well channel in the shell material.Type: ApplicationFiled: March 14, 2014Publication date: September 17, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: CARLOS H. DIAZ, CHUN-HSIUNG LIN, HUI-CHENG CHANG, SYUN-MING JANG, CHIEN-HSUN WANG, MAO-LIN HUANG
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Publication number: 20150255306Abstract: A nanowire field effect transistor (FET) device and method for forming the same is disclosed. The device comprises: a semiconductor substrate; a device layer including a source region and a drain region connected by a suspended nanowire channel; and etch stop layers respectively arranged beneath the source region and the drain region, the etch stop layers forming support structures interposed between the semiconductor substrate and the source and drain regions. The suspended nanowire channel is formed by etching a sacrificial material disposed beneath the suspended nanowire channel and between the etch stop layers. The etching is selective to the sacrificial material to prevent the removal of the etch stop layers beneath the source region and the drain region.Type: ApplicationFiled: May 26, 2015Publication date: September 10, 2015Inventors: CHIEN-HSUN WANG, MAO-LIN HUANG, CHUN-HSIUNG LIN, JEAN-PIERRE COLINGE
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Publication number: 20150228721Abstract: According to an exemplary embodiment, a method of forming a fin structure is provided. The method includes the following operations: etching a first dielectric layer to form at least one recess and a first core portion of a fin core; form an oxide layer as a shallow trench isolation layer in the recess; etching back the oxide layer to expose a portion of the fin core; and forming a fin shell to cover a sidewall of the exposed portion of the fin core.Type: ApplicationFiled: February 13, 2014Publication date: August 13, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: CHUN-HSIUNG LIN, CARLOS H. DIAZ, HUI-CHENG CHANG, SYUN-MING JANG, MAO-LIN HUANG, CHIEN-HSUN WANG
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Patent number: 9048301Abstract: A transistor device and method for forming a nanowire field effect transistor (FET) device are provided. A device layer including a source region and a drain region is formed, where the source region and the drain region are connected by a suspended nanowire channel. Etch stop layers are formed beneath the source region and the drain region. The etch stop layers comprise support structures interposed between a semiconductor substrate and the source and drain regions. The suspended nanowire channel is formed by etching a sacrificial material beneath the suspended nanowire channel. The etching is selective to the sacrificial material to prevent the removal of the etch stop layers beneath the source region and the drain region.Type: GrantFiled: October 16, 2013Date of Patent: June 2, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chien-Hsun Wang, Mao-Lin Huang, Chun-Hsiung Lin, Jean-Pierre Colinge
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Publication number: 20150129938Abstract: A semiconductor devices and method of formation are provided herein. A semiconductor device includes a gate structure over a channel and an active region adjacent the channel. The active region includes a repaired doped region and a growth region over the repaired doped region. The repaired doped region includes a first dopant and a second dopant, where the second dopant is from the growth region. A method of forming a semiconductor device includes increasing a temperature during exposure to at least one of dopant(s) or agent(s) to form an active region adjacent a channel, where the active region includes a repaired doped region and a growth region over the repaired doped region.Type: ApplicationFiled: November 8, 2013Publication date: May 14, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Mao-Lin Huang, Chien-Hsun Wang, Chun-Hsiung Lin, Meng-Ku Chen, Li-Ting Wang, Hung-Ta Lin
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Publication number: 20150129981Abstract: A method for forming a semiconductor device having a fin-type channel is provided. The method may include the following operations: forming a first buffer layer over a substrate; forming a first dielectric layer over the first buffer layer; patterning the first dielectric layer over the first buffer layer; forming a barrier layer over the first buffer layer; forming a second dielectric layer over the barrier layer; patterning the second dielectric layer over the barrier layer; forming a channel layer over the barrier layer; and patterning the second dielectric layer, such that at least a portion of the channel layer protrudes to form the fin-type channel.Type: ApplicationFiled: November 14, 2013Publication date: May 14, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: CHIEN-HSUN WANG, CHUN-HSIUNG LIN, MAO-LIN HUANG
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Publication number: 20150108550Abstract: A method for forming a transistor is provided. The method includes: forming a channel layer over a substrate; patterning the channel layer to form a recess; and forming a source layer in the recess, such that at least a portion of the channel layer protrudes to form the fin-type channel.Type: ApplicationFiled: October 17, 2013Publication date: April 23, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: CHIEN-HSUN WANG, MAO-LIN HUANG, CHUN-HSIUNG LIN
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Publication number: 20150102287Abstract: A transistor device and method for forming a nanowire field effect transistor (FET) device are provided. A device layer including a source region and a drain region is formed, where the source region and the drain region are connected by a suspended nanowire channel. Etch stop layers are formed beneath the source region and the drain region. The etch stop layers comprise support structures interposed between a semiconductor substrate and the source and drain regions. The suspended nanowire channel is formed by etching a sacrificial material beneath the suspended nanowire channel. The etching is selective to the sacrificial material to prevent the removal of the etch stop layers beneath the source region and the drain region.Type: ApplicationFiled: October 16, 2013Publication date: April 16, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: CHIEN-HSUN WANG, MAO-LIN HUANG, CHUN-HSIUNG LIN, JEAN-PIERRE COLINGE
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Publication number: 20150069467Abstract: A transistor includes a gate terminal, a source terminal and a drain terminal. At least one of the source and drain terminals has a layered configuration that includes a terminal layer and an intervening layer. The terminal layer has a top surface and a bottom surface. The intervening layer is located within the terminal layer, between and spaced from the top and bottom surfaces, is oriented to be perpendicular to current flow, and is less than one tenth the thickness of the terminal layer. The terminal layer and the intervening layer include a common semiconductive compound and a common dopant, with a concentration of the dopant in the intervening layer being over ten times an average concentration of the dopant in the terminal layer.Type: ApplicationFiled: September 12, 2013Publication date: March 12, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: HUNG-TA LIN, MAO-LIN HUANG, LI-TING WANG, CHIEN-HSUN WANG, MENG-KU CHEN, CHUN-HSIUNG LIN, PANG-YEN TSAI, HUI-CHENG CHANG
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Patent number: 8859441Abstract: The present invention provides a system and method for manufacturing a semiconductor device including a substrate and a high-? dielectric layer on the substrate. The system comprises a modular track; a substrate-forming chamber connected with the modular track for forming the substrate; and an atomic layer deposition (ALD) chamber connected with the modular track for providing the high-? dielectric layer.Type: GrantFiled: April 5, 2012Date of Patent: October 14, 2014Inventors: Ming-Hwei Hong, Ray-Nien Kwo, Tun-Wen Pi, Mao-Lin Huang, Yu-Hsing Chang, Pen Chang, Chun-An Lin, Tsung-Da Lin
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Publication number: 20130267077Abstract: The present invention provides a system and method for manufacturing a semiconductor device including a substrate and a high-? dielectric layer on the substrate. The system comprises a modular track; a substrate-forming chamber connected with the modular track for forming the substrate; and an atomic layer deposition (ALD) chamber connected with the modular track for providing the high-? dielectric layer.Type: ApplicationFiled: April 5, 2012Publication date: October 10, 2013Inventors: Ming-Hwei Hong, Ray-Nien Kwo, Tun-Wen Pi, Mao-Lin Huang, Yu-Hsing Chang, Pen Chang, Chun-An Lin, Tsung-Da Lin
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Patent number: 7773512Abstract: A bandwidth control method is adapted for use in a network device having a system clock. The network device has a register for storing a transmittable data amount to control bandwidth. The method includes: calculating a number of elapsed periods of the system clock so as to change a counting value every predetermined time interval, the counting value being cyclic within a specific range; adjusting the transmittable data amount in the register by a first unit amount when the counting value reaches a first count value; and adjusting the transmittable data amount in the register by a second unit amount after adjusting the transmittable data amount by the first unit amount and elapse of the predetermined time interval and when the counting value corresponds to a second count value. The first count value is different from the second count value, and the first unit amount is different from the second unit amount.Type: GrantFiled: February 15, 2008Date of Patent: August 10, 2010Assignee: Realtek Semiconductor CorporationInventors: Mao-Lin Huang, Yi-Lun Chen, Jin-Ru Chen
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Publication number: 20080198750Abstract: A bandwidth control method is adapted for use in a network device having a system clock. The network device has a register for storing a transmittable data amount to control bandwidth. The method includes: calculating a number of elapsed periods of the system clock so as to change a counting value every predetermined time interval, the counting value being cyclic within a specific range; adjusting the transmittable data amount in the register by a first unit amount when the counting value reaches a first count value; and adjusting the transmittable data amount in the register by a second unit amount after adjusting the transmittable data amount by the first unit amount and elapse of the predetermined time interval and when the counting value corresponds to a second count value. The first count value is different from the second count value, and the first unit amount is different from the second unit amount.Type: ApplicationFiled: February 15, 2008Publication date: August 21, 2008Inventors: Mao-Lin Huang, Yi-Lun Chen, Jin-Ru Chen
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Publication number: 20070009364Abstract: A blade of a ceiling fan includes a first flat end fixed to a blade bracket and a second end which includes an activation portion which includes a convex protruding from a top of the second end of the blade and a concavity is defined in an underside of the activation portion. Two sides of the activation portion are on a common horizontal surface with the first end of the blade. An angle between the horizontal surface and the convex is in a range of 15° to 20°. The blade generates stronger airflow with less resistance.Type: ApplicationFiled: July 8, 2005Publication date: January 11, 2007Inventor: Mao-Lin Huang