Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor layers and second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers are separated and stacked up, and a thickness of each second semiconductor layer is less than a thickness of each first semiconductor layer; a first interfacial layer around each first semiconductor layer; a second interfacial layer around each second semiconductor layer; a first dipole gate dielectric layer around each first semiconductor layer and over the first interfacial layer; a second dipole gate dielectric layer around each second semiconductor layer and over the second interfacial layer; a first gate electrode around each first semiconductor layer and over the first dipole gate dielectric layer; and a second gate electrode around each second semiconductor layer and over the second dipole gate dielectric layer.

Abstract: A method for forming a semiconductor arrangement comprises forming a first fin in a semiconductor layer. A first gate dielectric layer includes a first high-k material is formed over the first fin. A first sacrificial gate electrode is formed over the first fin. A dielectric layer is formed adjacent the first sacrificial gate electrode and over the first fin. The first sacrificial gate electrode is removed to define a first gate cavity in the dielectric layer. A second gate dielectric layer including a second dielectric material different than the first high-k material is formed over the first gate dielectric layer in the first gate cavity. A first gate electrode is formed in the first gate cavity over the second gate dielectric layer.

Abstract: A semiconductor having a first gate-all-around (GAA) transistor, a second GAA transistor, and a third GAA transistor is provided. The first (GAA) transistor includes a first plurality of channel members, a gate dielectric layer over the first plurality of channel members, a first work function layer over the gate dielectric layer, and a glue layer over the first work function layer. The second GAA transistor include a second plurality of channel members, the gate dielectric layer over the second plurality of channel members, and a second work function layer over the gate dielectric layer, the first work function layer over and in contact with the second work function layer, and the glue layer over the first work function layer. The third GAA transistor includes a third plurality of channel members, the gate dielectric layer over the third plurality of channel members, and the glue layer over the gate dielectric layer.

Abstract: A method for forming a semiconductor arrangement comprises forming a first fin in a semiconductor layer. A first gate dielectric layer includes a first high-k material is formed over the first fin. A first sacrificial gate electrode is formed over the first fin. A dielectric layer is formed adjacent the first sacrificial gate electrode and over the first fin. The first sacrificial gate electrode is removed to define a first gate cavity in the dielectric layer. A second gate dielectric layer including a second dielectric material different than the first high-k material is formed over the first gate dielectric layer in the first gate cavity. A first gate electrode is formed in the first gate cavity over the second gate dielectric layer.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first nanosheet field effect transistor (NSFET). The first NSFET includes a first nanosheet channel structure arranged over a substrate, a second nanosheet channel structure arranged directly over the first nanosheet channel structure, and a first gate electrode structure. The first and second nanosheet channel structures extend in parallel between first and second source/drain regions. The first gate electrode structure includes a first conductive ring and a second conductive ring that completely surround outer sidewalls of the first nanosheet channel structure and the second nanosheet channel structure, respectively, and that comprise a first material.

Abstract: In some embodiments, the present disclosure relates to an integrated chip including first, second, and third nanosheet field effect transistors (NSFETs) arranged over a substrate. The first NSFET has a first threshold voltage and includes first nanosheet channel structures embedded in a first gate electrode layer. The first nanosheet channel structures extend from a first source/drain region to a second source/drain region. The second NSFET has a second threshold voltage different than the first threshold voltage and includes second nanosheet channel structures embedded in a second gate electrode layer. The second nanosheet channel structures extend from a third source/drain region to a fourth source/drain region. The third NSFET has a third threshold voltage different than the second threshold voltage and includes third nanosheet channel structures embedded in a third gate electrode layer. The third nanosheet channel structures extend from a fifth source/drain region to a sixth source/drain region.

Abstract: A semiconductor device according to an embodiment includes a first gate-all-around (GAA) transistor and a second GAA transistor. The first GAA transistor includes a first plurality of channel members, a first interfacial layer over the first plurality of channel members, a first hafnium-containing dielectric layer over the first interfacial layer, and a metal gate electrode layer over the first hafnium-containing dielectric layer. The second GAA transistor includes a second plurality of channel members, a second interfacial layer over the second plurality of channel members, a second hafnium-containing dielectric layer over the second interfacial layer, and the metal gate electrode layer over the second hafnium-containing dielectric layer. A first thickness of the first interfacial layer is greater than a second thickness of the second interfacial layer. A third thickness of the first hafnium-containing dielectric layer is smaller than a fourth thickness of the second hafnium-containing dielectric layer.

Abstract: A semiconductor structure includes a substrate including a first region and a second region, a first FET device disposed in the first region, and a second FET device disposed in the second region. The first FET device includes a fin structure, a first work function metal layer disposed over the fin structure, and a high-k gate dielectric layer between the first work function metal layer and the fin structure. The second FET device includes a plurality of nanosheets stacked over the substrate and separated from each other, a second work function metal layer surrounding each of the nanosheets, and the high-k gate dielectric layer between the second work function metal layer and each of the nanosheets. In some embodiments, the fin structure has a first width, each of the nanosheets has a second width, and the second width is greater than the first width.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.

Abstract: A semiconductor device is provided. The semiconductor device includes a plurality of first semiconductor nanosheets spaced apart from each other and in a p-type device region, and a plurality of second semiconductor nanosheets spaced apart from each other and in an n-type device region. The semiconductor device includes an isolation structure formed at a boundary between the p-type and n-type device regions, and a first hard mask layer formed over the first semiconductor nanosheets. The semiconductor device also includes a second hard mask layer formed over the second semiconductor nanosheets, and a p-type work function layer surrounding each of the first semiconductor nanosheets and the first hard mask layer.

Abstract: A method includes depositing a first conductive material on a first-type channel stack and a second-type channel stack, the first conductive material having a first workfunction, the first conductive material being formed between multiple layers of both the first-type channel stack and the second-type channel stack. The method further includes partially removing the first conductive material from the second-type channel stack such that the first conductive material remains between the multiple layers of both the first-type channel stack and the second-type channel stack and fully removing the first conductive material from the second-type channel stack.

Abstract: A method of fabricating semiconductor devices includes forming a plurality of first and second semiconductor nanosheets in p-type and n-type device regions, respectively. An n-type work function layer is deposited to surround each of the first and second semiconductor nanosheets. A passivation layer is deposited on the n-type work function layer to surround each of the first and second semiconductor nanosheets. A patterned mask is formed on the passivation layer in the n-type device region, and the n-type work function layer and the passivation layer in the p-type device region are removed in an etching process using the patterned mask as an etching mask. Then, the patterned mask is removed, and a p-type work function layer is deposited to surround the first semiconductor nanosheets and to cover the passivation layer.

Abstract: A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate stack to form a opening in the dielectric layer, forming a metal layer extending into the opening, and etching back the metal layer. The remaining portions of the metal layer in the opening have edges lower than a top surface of the dielectric layer. A conductive layer is selectively deposited in the opening. The conductive layer is over the metal layer, and the metal layer and the conductive layer in combination form a replacement gate.

Abstract: A method of fabricating semiconductor devices includes forming a plurality of first and second nanosheets in p-type and n-type device regions, respectively. A p-type work function (PWF) layer is deposited to surround each of the first and second nanosheets. A first mask is formed on the PWF layer and not over the boundary between the p-type and n-type device regions, and then the PWF layer is etched in a first etching process to keep portions of the PWF layer between the second nanosheets. A second mask is formed on the PWF layer, and then the portions of the PWF layer between the second nanosheets are removed in a second etching process. An n-type work function layer is deposited in the n-type and the p-type device regions to surround each of the second nanosheets and on the PWF layer.

Abstract: A method of fabricating semiconductor devices includes forming a plurality of first and second nanosheets in p-type and n-type device regions, respectively. A p-type work function (PWF) layer is deposited to surround each of the first and second nanosheets. A first mask is formed on the PWF layer and not over the boundary between the p-type and n-type device regions, and then the PWF layer is etched in a first etching process to keep portions of the PWF layer between the second nanosheets. A second mask is formed on the PWF layer, and then the portions of the PWF layer between the second nanosheets are removed in a second etching process. An n-type work function layer is deposited in the n-type and the p-type device regions to surround each of the second nanosheets and on the PWF layer.

Abstract: A method for forming a semiconductor arrangement comprises forming a first fin in a semiconductor layer. A first gate dielectric layer includes a first high-k material is formed over the first fin. A first sacrificial gate electrode is formed over the first fin. A dielectric layer is formed adjacent the first sacrificial gate electrode and over the first fin. The first sacrificial gate electrode is removed to define a first gate cavity in the dielectric layer. A second gate dielectric layer including a second dielectric material different than the first high-k material is formed over the first gate dielectric layer in the first gate cavity. A first gate electrode is formed in the first gate cavity over the second gate dielectric layer.

Abstract: A method of integrated circuit (IC) fabrication includes exposing a plurality of channel regions including a p-type channel region and an n-type channel region; forming a gate dielectric layer over the exposed channel regions; and forming a work function metal (WFM) structure over the gate dielectric layer. The WFM structure includes a p-type WFM portion formed over the p-type channel region and an n-type WFM portion formed over the n-type channel region, and the p-type WFM portion is thinner than the n-type WFM portion. The method further includes forming a fill metal layer over the WFM structure such that the fill metal layer is in direct contact with both the p-type and n-type WFM portions.

Abstract: A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate stack to form a opening in the dielectric layer, forming a metal layer extending into the opening, and etching back the metal layer. The remaining portions of the metal layer in the opening have edges lower than a top surface of the dielectric layer. A conductive layer is selectively deposited in the opening. The conductive layer is over the metal layer, and the metal layer and the conductive layer in combination form a replacement gate.

Abstract: A method of fabricating an integrated circuit (IC) structure, includes forming a gate trench that exposes a portion of each of a plurality of fins and forming a threshold voltage (Vt) tuning dielectric layer in the gate trench over the plurality of fins. Properties of the Vt tuning dielectric layer are adjusted during the forming to achieve a different Vt for each of the plurality of fins. The method also includes forming a glue metal layer over the Vt tuning dielectric layer; and forming a fill metal layer over the glue metal layer. The fill metal layer has a substantially uniform thickness over top surfaces of the plurality of fins.

Abstract: Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a metal gate strip, gate spacers and a dielectric helmet. The substrate has fins. The metal gate strip is disposed across the fins and has a reversed T-shaped portion between two adjacent fins. The gate spacers are disposed on opposing sidewalls of the metal gate strip. A dielectric helmet is disposed over the metal gate strip.