Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for vertical tunneling field effect transistors (VFETs) having a dual liner bottom spacer. In a non-limiting embodiment of the invention, a first liner is formed on a top surface of a source or drain (S/D) region and sidewalls of a semiconductor fin. Portions of a spacer are removed to expose a first region and a second region of the first liner. The first region of the first liner is directly on the S/D region and the second region is over the semiconductor fin. A second liner is formed on the first liner. A first portion of the second liner is formed by selectively depositing dielectric material on the exposed first region and exposed second region of the first liner. The first liner and the second liner collectively define the dual liner bottom spacer.

Abstract: Sub-fin removal techniques for SOI like isolation in finFET devices are provided. In one aspect, a method for forming a finFET device includes: etching partial fins in a substrate, wherein the partial fins include top portions of fins of the finFET device; forming a bi-layer spacer on the top portions of the fins; complete etching of the fins in the substrate to form bottom portions of the fins of the finFET device; depositing an insulator between the fins; recessing the insulator enough to expose a region of the fins not covered by the bi-layer spacer; removing the exposed region of the fins to create a gap between the top and bottom portions of the fins; filling the gap with additional insulator. A method for forming a finFET device is also provided where placement of the fin spacer occurs after (rather than before) insulator deposition. A finFET device is also provided.

Abstract: Embodiments of the present invention are directed to techniques for providing a gate cut critical dimension (CD) shrink and active gate defect healing using selective deposition. The selective silicon on silicon deposition described herein effectively shrinks the gate cut CD to below lithographic limits and repairs any neighboring active gate damage resulting from a processing window misalignment by refilling the inadvertently removed sacrificial material. In a non-limiting embodiment of the invention, a sacrificial gate is formed over a shallow trench isolation region. A portion of the sacrificial gate is removed to expose a surface of the shallow trench isolation region. A semiconductor material is selectively deposited on exposed sidewalls of the sacrificial gate. A gate cut dielectric is formed on a portion of the shallow trench isolation between sidewalls of the semiconductor material.

Abstract: Semiconductor devices and methods for forming semiconductor devices include opening at least one contact via through a sacrificial material down to contacts. Sides of the at least one contact via are lined by selectively depositing a barrier on the sacrificial material, the barrier extending along sidewalls of the at least one contact via from a top surface of the sacrificial material down to a bottom surface of the sacrificial material proximal to the contacts such that the contacts remain exposed. A conductive material is deposited in the at least one contact via down to the contacts to form stacked contacts having the hard mask on sides thereof. The sacrificial material is removed.

Abstract: Embodiments of the invention are directed to a method that includes forming a fin over a major surface of a substrate. The fin includes an active fin region having a top fin surface and a fin sidewall. The top fin surface is substantially parallel with respect to the major surface, and the fin sidewall is substantially perpendicular with respect to the major surface. A gate is formed over and around a central portion of the fin, the gate having a bottom gate region and a top gate region. The bottom gate region is substantially below the top fin surface and includes a bottom gate region sidewall that is substantially parallel with respect to the fin sidewall. The top gate region is substantially above the top fin surface and includes a top gate region sidewall that is at an angle with respect to the major surface.

Abstract: Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.

Abstract: Semiconductor devices and methods for forming semiconductor devices include opening at least one contact via through a sacrificial material down to contacts. Sides of the at least one contact via are lined by selectively depositing a barrier on the sacrificial material, the barrier extending along sidewalls of the at least one contact via from a top surface of the sacrificial material down to a bottom surface of the sacrificial material proximal to the contacts such that the contacts remain exposed. A conductive material is deposited in the at least one contact via down to the contacts to form stacked contacts having the hard mask on sides thereof. The sacrificial material is removed.

Abstract: A method includes monitoring with at least one monitoring tool one or more activities associated with an enterprise. The method further includes analyzing data input from the at least one monitoring tool of the one or more activities, and determining, based on analytics performed on the data input and an implemented policy, when the one or more activities qualifies as an incident. A remedial response responsive to the incident is initiated. The monitoring, analyzing, determining and initiating steps are performed by at least one processing device including a processor operatively coupled to a memory.

Abstract: A method is presented for reducing dielectric gouging during etching processes of a magnetoresistive random access memory (MRAM) structure including an MRAM region and a non-MRAM region. The method includes forming protective layers in the MRAM region to preserve integrity of underlying dielectric layers, forming a bottom electrode in direct contact with the protective layers, and constructing an MRAM pillar over the bottom electrode, wherein the MRAM pillar includes a magnetic tunnel junction (MTJ) stack and a top electrode.

Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.

Abstract: A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure.

Abstract: A semiconductor device includes etching fins into a bulk substrate in an active region, the bulk substrate including an intermediate layer formed over a base layer and a first semiconductor layer formed over the intermediate layer such that the fins extend through the first semiconductor layer into the intermediate layer to form tapered bottom portions of the fins within the intermediate layer and vertical fin sidewalls of a semiconductor portions of the fins within the first semiconductor layer. A second semiconductor layer is formed around the tapered bottom portions below the semiconductor portions of the fins such that the second semiconductor layer covers the tapered bottom portions to form a top surface proximal to the semiconductor portions of the fins that is substantially parallel to a bottom surface of the top surface of the base layer. A gate structure is formed around the fins.

Abstract: A method of forming a power rail to semiconductor devices comprising removing a portion of the gate structure forming a gate cut trench separating a first active region of fin structures from a second active region of fin structures. A conformal etch stop layer is formed in the gate cut trench. A fill material is formed on the conformal etch stop layer filling at least a portion of the gate cut trench. The fill material has a composition that is etched selectively to the conformal etch stop layer. A power rail is formed in the gate cut trench. The conformal etch stop layer obstructs lateral etching during forming the power rail to substantially eliminate power rail to gate structure shorting.

Abstract: A method of forming a power rail to semiconductor devices comprising removing a portion of the gate structure forming a gate cut trench separating a first active region of fin structures from a second active region of fin structures. A conformal etch stop layer is formed in the gate cut trench. A fill material is formed on the conformal etch stop layer filling at least a portion of the gate cut trench. The fill material has a composition that is etched selectively to the conformal etch stop layer. A power rail is formed in the gate cut trench. The conformal etch stop layer obstructs lateral etching during forming the power rail to substantially eliminate power rail to gate structure shorting.

Abstract: A semiconductor device includes etching fins into a bulk substrate in an active region, the bulk substrate including an intermediate layer formed over a base layer and a first semiconductor layer formed over the intermediate layer such that the fins extend through the first semiconductor layer into the intermediate layer to form tapered bottom portions of the fins within the intermediate layer and vertical fin sidewalls of a semiconductor portions of the fins within the first semiconductor layer. A second semiconductor layer is formed around the tapered bottom portions below the semiconductor portions of the fins such that the second semiconductor layer covers the tapered bottom portions to form a top surface proximal to the semiconductor portions of the fins that is substantially parallel to a bottom surface of the top surface of the base layer. A gate structure is formed around the fins.

Abstract: Systems, computer-implemented methods, and computer program products that can facilitate elevator analytics and/or elevator optimization components are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a prediction component that can predict a current destination of an elevator passenger based on historical elevator usage data of the elevator passenger. The computer executable components can further comprise an assignment component that can assign the elevator passenger to an elevator based on the current destination.

Abstract: Embodiments of the present invention are directed to techniques for providing a gate cut critical dimension (CD) shrink and active gate defect healing using selective deposition. The selective silicon on silicon deposition described herein effectively shrinks the gate cut CD to below lithographic limits and repairs any neighboring active gate damage resulting from a processing window misalignment by refilling the inadvertently removed sacrificial material. In a non-limiting embodiment of the invention, a sacrificial gate is formed over a shallow trench isolation region. A portion of the sacrificial gate is removed to expose a surface of the shallow trench isolation region. A semiconductor material is selectively deposited on exposed sidewalls of the sacrificial gate. A gate cut dielectric is formed on a portion of the shallow trench isolation between sidewalls of the semiconductor material.

Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.

Abstract: A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure.

Abstract: According to embodiments of the present invention, a method of forming a self-aligned contact includes depositing an etch-stop liner on a surface of a gate cap and a contact region. A dielectric oxide layer is deposited onto the etch-stop layer. The dielectric oxide layer and the etch-stop liner are removed in a region above the contact region to form a removed region. A contact is deposited in the etched region.