Abstract: An automated canister reloading machine is able to reload a currency canister removed from an ATM. The reloading machine includes a supply of currency notes. The reloading machine can transfer currency notes from the supply into a storage area of the canister. The canister includes a memory that can store data representative of information concerning the canister, such as data representative of the type and number of currency notes held in the canister. The reloading machine is able to update the canister memory.

Abstract: A method, apparatus and computer program product implement optimized channel routing in an electronic package design. Electronic package physical design data are received. A physical design including a netlist including a plurality of nets is generated. Finite impulse response (FIR) driver coefficients are determined for each net in the netlist from simulation with generation of impulse responses of the netlist.

Abstract: A method, apparatus and computer program product are provided for implementing vertically coupled noise control through a mesh plane in an electronic package design. Electronic package physical design data are received. Instances of vertically coupled noise in the electronic package physical design data are identified. The identified instances of vertically coupled noise are quantified. Then the electronic package physical design data are modified to limit the vertically coupled noise.

Abstract: Method and system for routing fiber channel frames using a fiber channel switch element is provided. The method includes, inserting a time stamp value in a fiber channel frame that is received at a receive segment of the fiber channel switch element; determining if a timeout occurs after a frame arrives at a receive buffer; and processing the frame if the timeout occurred. The method also includes, determining if a delta time value, which provides an accumulated wait time for a frame, is present in frame data; subtracting the delta time stamp value from a global time stamp value and using the resulting time stamp value to determine frame timeout status in the fiber channel switch element. A timeout checker circuit declares a timeout after comparing a time stamp value that is inserted in a fiber channel frame with a programmed time out value and global counter value.

Abstract: The aural similarity measuring system and method provides a measure of the aural similarity between a target text (10) and one or more reference texts (11). Both the target text (10) and the reference texts (11) are converted into a string of phonemes (15) and then one or other of the phoneme strings are adjusted (16) so that both are equal in length. The phoneme strings are compared (12) and a score generated representative of the degree of similarity of the two phoneme strings. Finally, where there is a plurality of reference texts the similarity scores for each of the reference texts are ranked (13). With this aural similarity measuring system the analysis is automated thereby reducing risks of errors and omissions. Moreover, the system provides an objective measure of aural similarity enabling consistency of comparison in results and reproducibility of results.

Abstract: A heat sink apparatus having a plurality of chips attached to a first surface of a flexible carrier and a plurality of heat sink fins. One or more additional chips may be attached to a second surface of the flexible carrier. The flexible carrier has at least one complementary fold, the complementary fold having a counterclockwise fold and a clockwise fold as seen from the side. A first chip back surface of a first chip and a second chip back surface of a second chip are in thermal contact with a particular heat sink fin, that is, sharing the same heat sink fin. Thermal contact between the chips and heat sink fins is effected by force, by thermally conducting adhesive, by thermal grease, or by a combination of force and/or thermally conducting adhesive and/or thermal grease.

Abstract: An automated transaction machine (600) includes a note receiving storage and dispensing mechanism (624). The mechanism (624) includes a stacker mechanism (654). The stacker mechanism collects in a stack notes such as currency bills that are to be dispensed from the machine to a user, and the stack is then presented to the user from the machine. The stacker mechanism includes a stack support member (668), a flexible member (692) and spaced supports (694). Notes are engaged in supporting connection with the stack support member as the stack support member is rotated in a first rotational direction. After the stack is accumulated, rotation of the stack support member in an opposed rotational direction delivers the stack from the stacker mechanism.

Abstract: A power control method and power control structures are provided for managing a plurality of voltage islands of a functional chip. The power control structure includes a supply control and partition chip positioned between a substrate carrier and a functional chip including a plurality of voltage islands. The supply control and partition chip includes a plurality of first electrical connections to the functional chip including the plurality of voltage islands. The supply control and partition chip includes a plurality of second electrical connections to the substrate carrier. Power applied to predefined ones of the first electrical connections to the functional chip are selectively switched on and off by the supply control and partition chip.

Abstract: Balanced wiring delay within an electronic package is implemented. A plurality of nets in a net group is identified in the electronic package. A predefined structure is added to each net within the group. A balanced wiring delay customizing program systematically processes and reduces length of the nets until a set length balance is obtained for the net group.

Abstract: A power control method and power control structures are provided for managing a plurality of voltage islands of a functional chip. The power control structure includes a supply control and partition chip positioned between a substrate carrier and a functional chip including a plurality of voltage islands. The supply control and partition chip includes a plurality of first electrical connections to the functional chip including the plurality of voltage islands. The supply control and partition chip includes a plurality of second electrical connections to the substrate carrier. Power applied to predefined ones of the first electrical connections to the functional chip are selectively switched on and off by the supply control and partition chip.

Abstract: There is described a cache memory system including a first cache memory and a second cache memory. A first port is arranged to receive a request for a first item and determine whether the first item is in the first cache memory. A second port is arranged to receive a request for a second item and determine whether the second item is in the second cache memory. The system is arranged such that if the second item is determined not to be in the second cache memory, a request for the second item is sent to the first port. There is also described a method of accessing multiple items from a memory which has associated with it a first cache memory having a first port and a second cache memory having a second port.

Abstract: An automated transaction machine (600) includes a note receiving storage and dispensing mechanism (624). The mechanism (624) includes a stacker mechanism (654). The stacker mechanism collects in a stack notes such as currency bills that are to be dispensed from the machine to a user, and the stack is then presented to the user from the machine. The stacker mechanism includes a stack support member (668), a flexible member (692) and spaced supports (694). Notes are engaged in supporting connection with the stack support member as the stack support member is rotated in a first rotational direction. After the stack is accumulated, rotation of the stack support member in an opposed rotational direction delivers the stack from the stacker mechanism.

Abstract: A memory system having a memory controller and a memory. The memory controller is coupled to a processor and to the memory. The memory comprises one or more daisy chains of memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of the memory chips in the daisy chain of memory chips. Data to be written to a memory chip is sent as part of the address/command word, or is transferred on an outgoing data bus chain. Data read from a memory chip is transferred on an incoming data bus chain. A daisy chain of memory chips can include memory chips on multiple carriers, or the daisy chain of memory chips can all be attached to a single carrier.

Abstract: A computer system having a memory system, the memory system having a memory controller and a memory. The memory comprises one or more daisy chains of self timed memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of the memory chips in the daisy chain of memory chips. Data to be written to a memory chip is sent as part of the address/command word, or is transferred on an outgoing data bus chain. Data read from a memory chip is transferred on an incoming data bus chain. Access timing on each memory chip is determined by a self time block on each memory chip.

Abstract: A memory chip suitable for use in a daisy chain of memory chips. The memory chip receives an address/command word on a first input, determines if the address command word is directed to the memory chip; if so, the memory chip accesses an array on the memory chip respondent to the address/command word. If not, the memory chip re-drives the address/command word on a first output. Write data is received as part of the address/command word or from a first data bus port. Read data is read from the array or is received from a second data bus port for subsequent re-driving on the first data bus port. A bus clock is received and is used to receive and transmit information on the first input, the first output, the first data bus port and the second data bus port.

Abstract: A method and structure are provided for implementing component placement suspended within electrical pin grid array packages for enhanced electrical performance. A solder column grid array is coupled between a printed circuit board and a first level package. A component is connected between a predefined pair of adjacent columns in the solder column grid array suspended between the printed circuit board and the first level package.

Abstract: There is disclosed a data processor having a clustered architecture that comprises at least one branching cluster, at least one non-branching cluster and remote conditional branching control circuitry. Each of the clusters is capable of computing branch conditions, though only the branching cluster is operable to perform branch address computations. The remote conditional branching control circuitry, which is associated with each of the clusters, is operable in response to sensing a conditional branch instruction in a non-branching cluster to (i) cause the branching cluster to compute a branch address and a next program counter address,(ii) cause the non-branching cluster to compute a branch condition, and (iii) communicate the computed branch condition from the non-branching cluster to the branching cluster. The data processor then uses the computed branch condition to select one of the branch address or the next program counter address.

Abstract: An automated canister reloading machine is able to reload a currency canister removed from an ATM. The reloading machine includes a supply of currency notes. The reloading machine can transfer currency notes from the supply into a storage area of the canister. The canister includes a memory that can store data representative of information concerning the canister, such as data representative of the type and number of currency notes held in the canister. The reloading machine is able to update the canister memory.

Abstract: A memory chip having a data bus having a plurality of bits. The number of bits is apportioned between a read portion and a write portion. The write portion is dedicated to receiving data that is to be written into an array on the memory chip; the read portion is dedicated to driving data that has been read from the array on the memory chip. The apportionment is programmable. Apportionment can be specified by programming signal pins on the memory chip, connecting the signal pins to appropriate logical values. The apportionment can alternatively be specified by scanning apportionment information into the memory chip at bring up time. The apportionment and also alternatively be specified by receiving apportionment information in an address/command word.

Abstract: A memory chip suitable for use in a daisy chain of memory chips. The memory chip receives an address/command word on a first input, determines if the address command word is directed to the memory chip; if so, the memory chip accesses an array on the memory chip respondent to the address/command word. If not, the memory chip re-drives the address/command word on a first output. Write data is received as part of the address/command word or from a first data bus port. Read data is read from the array or is received from a second data bus port for subsequent re-driving on the first data bus port. A bus clock is received and is used to receive and transmit information on the first input, the first output, the first data bus port and the second data bus port.