Abstract: Amine stabilizing agents containing an azeotrope comprising water, an alcohol, and sodium hydride. Amine stabilizing agents containing water and a liquid silica hydroxide compound. Methods of making of amine stabilizing agents where solid silicon rock and sodium hydroxide are mixed with an ammonium/water solution to produce a green liquid in a first stage of the reaction. Alcohol is added and the alcohol fraction is separated from the non-alcohol fraction to produce an alcohol fraction product and a bottom fraction that is not soluble in alcohol or organics. The agents can be added to amines for stabilizing amines in anime processing of gases, in CO2 capture, in CO2 abatement systems and in other systems where amines are utilized to remove contaminants.

Abstract: An automated transaction machine (600) includes a note receiving storage and dispensing mechanism (624). The mechanism (624) includes a stacker mechanism (654). The stacker mechanism collects in a stack notes such as currency bills that are to be dispensed from the machine to a user, and the stack is then presented to the user from the machine. The stacker mechanism includes a stack support member (668), a flexible member (692) and spaced supports (694). Notes are engaged in supporting connection with the stack support member as the stack support member is rotated in a first rotational direction. After the stack is accumulated, rotation of the stack support member in an opposed rotational direction delivers the stack from the stacker mechanism.

Abstract: In order to disinfect and to detoxify a fluid, a photoreactor contains at least two light sources. One light source activates the catalytic function of a semiconductor material in the fluid to reduce the concentration of contaminants in the fluid, such as by breaking down organic contaminants into non-toxic compounds. A second light source acts directly on living biological entities to sterilize or kill them and thereby disinfect the fluid, and can also serve to activate a semiconductor photocatalyst that in turn causes further damage to biological contaminants. The semiconductor photocatalyst is desirably attached to an optically transmitting fiber substrate in the fluid. The second light source in one embodiment is external to the fluid and illuminates the photocatalyst through transmitting surfaces in a fluid containment vessel. The light sources can comprise respective sets of plural LEDs.

Abstract: There is disclosed a data processor having a clustered architecture that comprises at least one branching cluster, at least one non-branching cluster and remote conditional branching control circuitry. Each of the clusters is capable of computing branch conditions, though only the branching cluster is operable to perform branch address computations. The remote conditional branching control circuitry, which is associated with each of the clusters, is operable in response to sensing a conditional branch instruction in a non-branching cluster to (i) cause the branching cluster to compute a branch address and a next program counter address, (ii) cause the non-branching cluster to compute a branch condition, and (iii) communicate the computed branch condition from the non-branching cluster to the branching cluster. The data processor then uses the computed branch condition to select one of the branch address or the next program counter address.

Abstract: A processing system for accessing first and second data types. The first data type is data supplied from a peripheral and the second data type is randomly accessible data held in a data memory. The processing system includes: a processor for executing instructions; a stream register unit connected to supply data from the peripheral to the processor; and a FIFO. The FIFO is connected to receive data from the peripheral and connected to the stream register unit by a communication path, along which the received data can be supplied from the FIFO to the stream register unit. The Processing system also includes a memory bus connected between the data memory and the processor, across which the processor can access the randomly accessible data.

Abstract: A communications architecture utilizes modules arranged in a daisy-chain, each module supporting multiple input and output ports. Point-to-point links are arranged so that a first output link of each of multiple modules connects to the next module in the chain, and a second output link connects to a module after it, and inputs arranged similarly, so that any single module can be by-passed in the event of malfunction. Multiple chains may be cross-linked and/or serviced by hubs or chains of hubs. Preferably, the redundant links are used in a non-degraded operating mode to provide higher bandwidth and/or reduced latency of communication. The exemplary embodiment is a memory subsystem in which the modules are buffered memory chips.

Abstract: In many aspects, the systems and methods described herein include mattress assemblies with attached sensory devices. The mattress assembly comprises a mattress core, an attached headboard, a mattress cover at least partially enclosing the mattress core, and at least one customer assistance sensory device attached to at least one of the core, headboard, and cover. The customer assistance sensory device is configured to present at least one parameter of the mattress core or assembly as at least a visual signal. Visual signals may include one or more distinct colors, shapes, or graphic patterns that correspond to one or more parameter of the mattress core or assembly.

Abstract: A method and system for distributing credit using a fibre channel switch element is provided. The switch element includes, a wait threshold counter that is used to set up a status for a port that has to wait for certain duration to send a frame due to lack of buffer to buffer credit; a credit module that controls buffer to buffer credit for a transmit segment of the fibre channel switch element; and a virtual lane credit module with a counter that is incremented every time a frame assigned to a virtual lane is sent and decreased every time a VC_RDY is received. The method includes, determining if a VC_RDY primitive is received; and allocating credit to a virtual lane that is not at its maximum credit, after the VC_RDY primitive is received.

Abstract: Method and system for a network switch element is provided. The switch element includes a plurality of megaports, each megaport uniquely identified by a unique megaport address identifier for network addressing. Each megaport includes a plurality of operational ports, each operational port identified by a unique operational port address identifier. The switch element also includes a local crossbar for communication between the plurality of operational ports, and a shared logic module configured to provide common control of the plurality of operational ports within a megaport to allow operational ports to share resource of a single megaport to route network packets there between.

Abstract: A cash dispensing banking transaction machine that operates responsive to data bearing records includes a card reader that reads identifying data from a user card. The machine dispenses cash from a cash dispenser for a financial account without causing the card reader device to read data from a card corresponding to the financial account, when a determination indicates that a voice of the user included in an audio input signal to audio input device corresponds to a particular recognized user stored in a data store in correlated relation with the financial account.

Abstract: A heat sink apparatus having a plurality of chips attached to a first surface of a flexible carrier and a plurality of heat sink fins. One or more additional chips may be attached to a second surface of the flexible carrier. The flexible carrier has at least one complementary fold, the complementary fold having a counterclockwise fold and a clockwise fold as seen from the side. A first chip back surface of a first chip and a second chip back surface of a second chip are in thermal contact with a particular heat sink fin, that is, sharing the same heat sink fin. Thermal contact between the chips and heat sink fins is effected by force, by thermally conducting adhesive, by thermal grease, or by a combination of force and/or thermally conducting adhesive and/or thermal grease.

Abstract: A computer system having a memory system having a memory controller and a memory. The memory controller is coupled to a processor and to the memory. The memory comprises one or more daisy chains of memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of the memory chips in the daisy chain of memory chips. Data to be written to a memory chip is sent as part of the address/command word, or is transferred on an outgoing data bus chain. Data read from a memory chip is transferred on an incoming data bus chain. A daisy chain of memory chips can include memory chips on multiple carriers, or the daisy chain of memory chips can all be attached to a single carrier.

Abstract: A method and system for processing received and transmit data by an application specific integrated circuit (ASIC) from a network link. The method for received data includes swapping received data polarity if swap-polarity ability is set and swapping byte lanes for the received data if swap-lane ability is set. The method for transmit data includes swapping byte lanes for transmit data, if swap-byte lane ability is set and swapping data polarity if swap-polarity ability is set. The ASIC includes a network connector that receives and transmits data from the network link.

Abstract: A carrier having at least one self timed memory chip in a daisy chain of memory chips. A first carrier has at least a portion of a daisy chain of memory chips attached to the first carrier. An address/command bus input on the first carrier carries an address/command word to a first memory chip in the daisy chain of memory chips. If the first memory chip determines that the address/command word is not directed to the first memory chip, the first memory chip re-drives the address/command word to a second memory chip in the daisy chain of memory chips using a point to point address/command bus link. If there are no more memory chips on the first carrier, the address/command word is re-driven to an address/command bus off-carrier connector. An array on a memory chip has an access time dynamically determined by how fast the array can be accessed.

Abstract: A memory chip suitable for use in a daisy chain of memory chips. Timing of an array on the memory chip is dynamically determined by circuitry on the memory chip that tracks an access timing of the array. The memory chip is configured to receive an address/command word, determine if the address/command word is directed to the memory chip. If so, the array on the memory chip is accessed according to the address command word. If the address/command word is not directed to the memory chip, the memory chip re-drives the address/command word from an output of the memory chip.

Abstract: This invention utilizes silicon through via technology, to build a Toroid into the chip with the addition of a layer of magnetic material such as Nickel above and below the T-coil stacked multi-ring structure. This allows the connection between the inner via and an array of outer vias. This material is added on a BEOL metal layer or as an external coating on the finished silicon. Depending on the configuration and material used for the via, the inductance will increase approximately two orders of magnitude (e.g., by utilizing a nickel via core). Moreover, a ferrite material with proper thermal conduction properties is used in one embodiment.

Abstract: Method and system for routing fiber channel frames using a fiber channel switch element is provided. The method includes, inserting a time stamp value in a fiber channel frame that is received at a receive segment of the fibre channel switch element; determining if a timeout occurs after a frame arrives at a receive buffer; and processing the frame if the timeout occurred. The method also includes, determining if a delta time value, which provides an accumulated wait time for a frame, is present in frame data; subtracting the delta time stamp value from a global time stamp value and using the resulting time stamp value to determine frame timeout status in the fiber channel switch element. A timeout checker circuit declares a timeout after comparing a time stamp value that is inserted in a fiber channel frame with a programmed time out value and a global counter value.

Abstract: A method and system for distributing credit using a fiber channel switch element is provided. The switch element includes, a wait threshold counter that is used to set up a status for a port that has to wait for certain duration to send a frame due to lack of buffer to buffer credit; a credit module that controls buffer to buffer credit for a transmit segment of the fiber channel switch element; and a virtual lane credit module with a counter that is incremented every time a frame assigned to a virtual lane is sent and decreased every time a VC_RDY is received. The method includes, determining if a VC_RDY primitive is received; and allocating credit to a virtual lane that is not at its maximum credit, after the VC_RDY primitive is received.

Abstract: The aural similarity measuring system and method provides a measure of the aural similarity between a target text (10) and one or more reference texts (11). Both the target text (10) and the reference texts (11) are converted into a string of phonemes (15) and then one or other of the phoneme strings are adjusted (16) so that both are equal in length. The phoneme strings are compared (12) and a score generated representative of the degree of similarity of the two phoneme strings. Finally, where there is a plurality of reference texts the similarity scores for each of the reference texts are ranked (13). With this aural similarity measuring system the analysis is automated thereby reducing risks of errors and omissions. Moreover, the system provides an objective measure of aural similarity enabling consistency of comparison in results and reproducibility of results.

Abstract: A method and apparatus implement cache coherency and reduced latency using multiple controllers for a memory system, and a design structure is provided on which the subject circuit resides. A first memory controller uses a first memory as its primary address space, for storage and fetches. A second memory controller is also connected to the first memory. A second memory controller uses a second memory as its primary address space, for storage and fetches. The first memory controller is also connected to the second memory. The first memory controller and the second memory controller, for example, are connected together by a processor communications bus. A request and send sequence of the invention sends data directly to a requesting memory controller eliminating the need to re-route data back through a responding controller, and improving the latency of the data transfer.