Patents by Inventor Mark A. Owens

Mark A. Owens has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DAISY CHAINABLE SELF TIMED MEMORY CHIP
    Publication number: 20080028161
    Abstract: A memory chip suitable for use in a daisy chain of memory chips. Timing of an array on the memory chip is dynamically determined by circuitry on the memory chip that tracks an access timing of the array. The memory chip is configured to receive an address/command word, determine if the address/command word is directed to the memory chip. If so, the array on the memory chip is accessed according to the address command word. If the address/command word is not directed to the memory chip, the memory chip re-drives the address/command word from an output of the memory chip.
    Type: Application
    Filed: July 26, 2006
    Publication date: January 31, 2008
    Inventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
  • DAISY CHAINED MEMORY SYSTEM
    Publication number: 20080025129
    Abstract: A memory system having a memory controller and a memory. The memory controller is coupled to a processor and to the memory. The memory comprises one or more daisy chains of memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of the memory chips in the daisy chain of memory chips. Data to be written to a memory chip is sent as part of the address/command word, or is transferred on an outgoing data bus chain. Data read from a memory chip is transferred on an incoming data bus chain. A daisy chain of memory chips can include memory chips on multiple carriers, or the daisy chain of memory chips can all be attached to a single carrier.
    Type: Application
    Filed: July 26, 2006
    Publication date: January 31, 2008
    Inventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
  • COMPUTER SYSTEM HAVING DAISY CHAINED SELF TIMED MEMORY CHIPS
    Publication number: 20080025130
    Abstract: A computer system having a memory system, the memory system having a memory controller and a memory. The memory comprises one or more daisy chains of self timed memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of the memory chips in the daisy chain of memory chips. Data to be written to a memory chip is sent as part of the address/command word, or is transferred on an outgoing data bus chain. Data read from a memory chip is transferred on an incoming data bus chain. Access timing on each memory chip is determined by a self time block on each memory chip.
    Type: Application
    Filed: July 26, 2006
    Publication date: January 31, 2008
    Inventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
  • Memory System Having an Apportionable Data Bus and Daisy Chained Memory Chips
    Publication number: 20080028126
    Abstract: A memory system having a memory controller and a daisy chain of memory chips. The memory controller is coupled to memory chips in the daisy chain of memory chips by an address/command bus chain. The memory controller is coupled to memory chips in the daisy chain of memory chips by a data bus chain having a number of data bus bits. The data bus chain has a first portion of data bus bits dedicated to transmitting write data from the memory controller to a memory chip. The data bus chain has a second portion of data bus bits dedicated to transmitting read data from a memory chip to the memory controller. Apportionment of data bus bits between the first portion and the second portion is programmable. Programming is done by pin connection, scanning of a value, or by request from a processor coupled to the memory controller.
    Type: Application
    Filed: July 26, 2006
    Publication date: January 31, 2008
    Inventors: Gerald Keith Bartley, Darryl John Becker, John Michael Borkenhagen, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
  • CARRIER HAVING DAISY CHAIN OF SELF TIMED MEMORY CHIPS
    Publication number: 20080028160
    Abstract: A carrier having at least one self timed memory chip in a daisy chain of memory chips. A first carrier has at least a portion of a daisy chain of memory chips attached to the first carrier. An address/command bus input on the first carrier carries an address/command word to a first memory chip in the daisy chain of memory chips. If the first memory chip determines that the address/command word is not directed to the first memory chip, the first memory chip re-drives the address/command word to a second memory chip in the daisy chain of memory chips using a point to point address/command bus link. If there are no more memory chips on the first carrier, the address/command word is re-driven to an address/command bus off-carrier connector. An array on a memory chip has an access time dynamically determined by how fast the array can be accessed.
    Type: Application
    Filed: July 26, 2006
    Publication date: January 31, 2008
    Inventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
  • Computer System Having an Apportionable Data Bus
    Publication number: 20080028125
    Abstract: A memory system having a data bus coupling a memory controller and a memory. The data bus has a number of data bus bits. The data bus is programmably apportioned to a first portion dedicated to transmitting data from the memory controller to the memory and a second portion dedicated to transmitting data from the memory to the memory controller. The apportionment can be assigned by suitable connection of pins on a memory chip in the memory and the memory controller to logical values. Alternatively, the apportionment can be scanned into the memory controller and the memory at bring up time. In another alternative, the apportionment can be changed by suspending data transfer and dynamically changing the sizes of the first portion and the second portion.
    Type: Application
    Filed: July 26, 2006
    Publication date: January 31, 2008
    Inventors: Gerald Keith Bartley, Darryl John Becker, John Michael Borkenhagen, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
  • CARRIER HAVING DAISY CHAINED MEMORY CHIPS
    Publication number: 20080028159
    Abstract: A carrier having at least one memory chip in a daisy chain of memory chips. A first carrier has at least a portion of an entire daisy chain of memory chips attached to the first carrier. An address/command bus input on the first carrier carries an address/command word to a first memory chip in the daisy chain of memory chips. If the first memory chip determines that the address/command word is not directed to the first memory chip, the first memory chip re-drives the address/command word to a second memory chip in the daisy chain of memory chips using a point to point address/command bus link. If there are no more memory chips on the first carrier, the address/command word is re-driven to a memory chip on a second carrier.
    Type: Application
    Filed: July 26, 2006
    Publication date: January 31, 2008
    Inventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
  • Self Timed Memory Chip Having an Apportionable Data Bus
    Publication number: 20080028175
    Abstract: A self timed memory chip having an apportionable data bus. Access timing to an array on the memory chip is dynamically determined by circuitry on the memory chip. A ring oscillator on the memory chip has a frequency that is indicative of how fast an array on the memory chip can be accessed. The ring oscillator includes a bit line that is periodically charged and a memory element that subsequently discharges the bit line. The memory chip has a data bus interface having a number of bits. The data bus interface has a first number of bits apportioned to write data and a second number of bits apportioned to read data. The first number of bits and the second number of bits is programmable.
    Type: Application
    Filed: July 26, 2006
    Publication date: January 31, 2008
    Inventors: Gerald Keith Bartley, Darryl John Becker, John Michael Borkenhagen, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
  • Memory Controller for Daisy Chained Self Timed Memory Chips
    Publication number: 20080028177
    Abstract: A memory controller for controlling a daisy chain of self timed memory chips. The memory controller has information as to how long each self timed memory chip in the daisy chain of memory chips takes to make a read access and a write access to an array on the self timed memory chip. The memory controller determines current access time information on a memory chip by sending a command to the memory chip. The memory chip returns a data word containing the current access time information. Alternatively, the memory controller transmits an address/command word to the memory chip and, after completing an access, transmits a responsive data word to the memory controller. The memory controller determines the access time information using the interval from transmission of the address/command word to reception of the responsive data word.
    Type: Application
    Filed: July 26, 2006
    Publication date: January 31, 2008
    Inventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
  • Computer System Having Daisy Chained Memory Chips
    Publication number: 20080028123
    Abstract: A computer system having a memory system having a memory controller and a memory. The memory controller is coupled to a processor and to the memory. The memory comprises one or more daisy chains of memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of the memory chips in the daisy chain of memory chips. Data to be written to a memory chip is sent as part of the address/command word, or is transferred on an outgoing data bus chain. Data read from a memory chip is transferred on an incoming data bus chain. A daisy chain of memory chips can include memory chips on multiple carriers, or the daisy chain of memory chips can all be attached to a single carrier.
    Type: Application
    Filed: July 26, 2006
    Publication date: January 31, 2008
    Inventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
  • MEMORY SYSTEM HAVING SELF TIMED DAISY CHAINED MEMORY CHIPS
    Publication number: 20080028176
    Abstract: A memory system having a memory controller and a memory. The memory comprises one or more daisy chains of self timed memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of the memory chips in the daisy chain of memory chips. Data to be written to a memory chip is sent as part of the address/command word, or is transferred on an outgoing data bus chain. Data read from a memory chip is transferred on an incoming data bus chain. Access timing on a memory chip is determined by a self time block on the memory chip.
    Type: Application
    Filed: July 26, 2006
    Publication date: January 31, 2008
    Inventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
  • Memory Controller For Daisy Chained Memory Chips
    Publication number: 20080028158
    Abstract: A memory controller configured to control a daisy chain of memory chips. The memory controller receives read and write requests from a processor, determines a daisy chain of memory chips that the request is directed to, determines which memory chip in the chain of memory chips the request is directed to, and transmits an address/command word recognizable by the correct memory chip. The memory controller sends write data words to the daisy chain of memory chips that can be associated by the correct memory chip for writing into the correct memory chip. The memory controller receives read data words from the daisy chain of memory chips and returns the read data to the processor. The memory controller transmits a bus clock to the daisy chain of memory chips for controlling transmission of address/command words and data words.
    Type: Application
    Filed: July 26, 2006
    Publication date: January 31, 2008
    Inventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
  • Method and system for controlling packet flow in networks
    Patent number: 7319669
    Abstract: A system and method for transmitting and bundling network packets is provided. The incoming network packet size is determined and if the remote buffer space is sufficient to hold the network packet it is transmitted to the destination port. If the remote buffer space is not enough to hold the network packet it is discarded. The system includes an arbitration module that receives remote buffer space information and transmits the network packet if the remote buffer space has enough space to hold the packet. The arbitration module also determines if a second network packet is from a same source port having a same source virtual lane, and has the same destination virtual lane (bundling conditions). If the second network packet meets the bundling conditions, then it is transmitted after the first network packet, even if other packets were received before the second network packet.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: January 15, 2008
    Assignee: QLogic, Corporation
    Inventors: James A. Kunz, Leonard W. Haseman, Mark A. Owen, William J. Gustafson
  • Method, Structures and Computer Program Product for Implementing Enhanced Wiring Capability for Electronic Laminate Packages
    Publication number: 20070294653
    Abstract: A method, structures and computer program product are provided for implementing enhanced wiring capability for electronic laminate packages. Electronic package physical design data are received. Instances of line width and space limit violations in the electronic package physical design data are identified. The identified instances of line width and space limit violations are evaluated using predefined qualified options and tolerance limitations and the electronic package physical design data are modified to optimize shapes to replace the instances of line width and space limit violations.
    Type: Application
    Filed: June 14, 2006
    Publication date: December 20, 2007
    Inventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson, Trevor Joseph Timpane
  • Methods and systems relating to solid state light sources for use in industrial processes
    Publication number: 20070278504
    Abstract: Methods and systems relating to solid state light sources for use in industrial processes.
    Type: Application
    Filed: January 26, 2006
    Publication date: December 6, 2007
    Inventors: Roland Jasmin, Mark Owen, Alex Schreiner, Duwayne Anderson
  • Adjustable trim for sloped ceiling recessed downlight
    Patent number: 7303314
    Abstract: A two piece adjustable trim for a sloped ceiling recessed downlight wherein the two piece trim has an upper element and a lower element hingedly connected to each other. A standard frame in housing may be utilized to receive the two piece rotatable trim, the trim and a lower element affixed to the mounting frame and pivotable relative to an upper trim element.
    Type: Grant
    Filed: October 13, 2005
    Date of Patent: December 4, 2007
    Assignee: Genlyte Thomas Group, LLC
    Inventor: Mark Owen Jones
  • RF communication of data between currency canister and automated banking machine
    Publication number: 20070194106
    Abstract: An automated canister reloading machine is able to reload a currency canister removed from an ATM. The reloading machine includes a supply of currency notes. The reloading machine can transfer currency notes from the supply into a storage area of the canister. The canister includes a memory that can store data representative of information concerning the canister, such as data representative of the type and number of currency notes held in the canister. The reloading machine is able to update the canister memory.
    Type: Application
    Filed: April 23, 2007
    Publication date: August 23, 2007
    Applicant: Diebold, Incorporated
    Inventors: Matthew Force, H. Graef, Robert Bowser, Jeffrey Eastman, Michael Harty, Andrew Junkins, Michael Lindroos, Mark Owens, Mike Ryan, Alan Looney, Roy Shirah
  • Computer system architecture for a processor connected to a high speed bus transceiver
    Patent number: 7234017
    Abstract: A high speed computer processor system has a high speed interface for a graphics processor. A preferred embodiment combines a PowerPC microprocessor called the Giga-Processor Ultralite (GPUL) 110 from International Business Machines Corporation (IBM) with a high speed interface on a multi-chip module.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: June 19, 2007
    Assignee: International Business Machines Corporation
    Inventors: Giora Biran, Matthew Adam Cushing, Robert Allen Drehmel, Allen James Gavin, Mark E. Kautzman, Jamie Randall Kuesel, Ming-I Mark Lin, David Arnold Luick, James Anthony Marcella, Mark Owen Maxson, Eric Oliver Mejdrich, Adam James Muff, Clarence Rosser Ogilvie, Charles S. Woodruff
  • Embedded probe-enabling socket with integral probe structures
    Patent number: 7202685
    Abstract: A method of testing and an embedded probe-enabling socket are provided for implementing debug and testing functions. The socket includes an integral probe structure enabling Top Side of the Module (TSM) signal probing. The socket includes a substrate with a topside including a plurality of probe pads. A TSM socket frame includes a plurality of probe pins electrically connecting to respective probe pads on the substrate topside. The probe pins are electrically connected with a respective signal to be monitored.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: April 10, 2007
    Assignee: International Business Machines Corporation
    Inventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
  • High density led array
    Publication number: 20070051964
    Abstract: A dense array of semiconductor devices having an array of micro-reflectors, the micro-reflectors having characteristics that enhance dense packing of the array in balance with collection and collimation of the array's radiant output.
    Type: Application
    Filed: May 12, 2006
    Publication date: March 8, 2007
    Inventors: Mark Owen, Duwayne Anderson