Abstract: A structure and an improved isolation trench between active regions within the semiconductor substrate involves forming on a silicon substrate and forming a nitride layer on the pad layer. Thereafter, a photoresist layer is patterned on the silicon nitride layer such that regions of the nitride layer are exposed where an isolation trench will subsequently be formed. Next, the exposed regions of the nitride layer and the pad layer situated below the exposed regions of the nitride layer are etched away to expose regions of the silicon substrate. Subsequently, isolation trenches are etched into the silicon substrate with a dry etch process. A trench liner is then formed and nitrogen incorporated into a portion of the trench liner to form an oxynitride layer. After formation of the oxynitride layer, the trench is filled with a dielectric preferably comprised of a CVD oxide. Thereafter, the CVD fill dielectric is planarized and the nitride layer is stripped away.

Abstract: An integrated circuit is provided in which nitrogen is incorporated into the gate dielectric and transistor gate. A method for forming the integrated circuit preferably comprises the providing of a semiconductor substrate that has a p-well and a laterally displaced n-well, each including a channel region laterally displaced between a pair of source/drain regions. Preferably, the semiconductor substrate has a resistivity of approximately 10 to 15 &OHgr;-cm. A dielectric layer is formed on an upper surface of the semiconductor substrate. The formation of the dielectric layer preferably comprises a thermal oxidation performed at a temperature of approximately 600 to 900° C. and the resulting thermal oxide has a thickness less than approximately 50 angstroms. A conductive gate layer is then formed on the dielectric layer.

Abstract: A transistor is provided having a metal silicide gate spaced above a semiconductor substrate by a high-dielectric-constant ceramic gate dielectric. The entire gate conductor is preferably composed of a metal silicide. In an embodiment, the metal silicide is cobalt silicide and the ceramic gate dielectric is barium strontium titanate, lead lanthanum zirconate titanate barium zirconate titanate, cerium oxide, or tin oxide. In another embodiment, the ceramic gate dielectric has nitrogen atoms incorporated therein. The transistor may also include dielectric spacers adjacent opposed sidewall surfaces of the gate conductor, lightly doped drain regions arranged underneath the spacers, and source and drain regions arranged adjacent the lightly doped drain regions.

Abstract: The present disclosure relates to a chemical vapor deposition system including a chemical vapor deposition chamber, and a circlet wafer positioned within the chemical vapor deposition chamber. The circlet wafer is mounted on a rotatable member that at least partially extends through an opening of the wafer. A drive mechanism is used to rotate the rotatable member and the circlet wafer. The system also includes a gas injector for injecting reactive gases toward the circlet wafer. The present disclosure also relates to a chemical vapor deposition system including a chemical vapor deposition chamber, a wafer positioned within the chemical vapor deposition chamber, and a gas injector for injecting first and second reactive gases toward the wafer. The gas injector includes a mixing region for mixing the first and second reactive gases before the first and second reactive gases are discharged from the gas injector.

Abstract: The present invention generally provides a semiconductor device and fabrication process in which gate electrode formation is integrated with the formation of isolation regions. Consistent with one embodiment of the invention, the semiconductor device is formed by forming at least two adjacent gate electrode stacks of the substrate. A layer of dielectric material is formed over regions of the substrate between the two adjacent gate electrode stacks and portions of the dielectric material layer are selectively removed to leave an isolation block of the dielectric material between the two adjacent gate electrode stacks. The gate electrode stacks may, for example, have a thickness ranging from about 2,500 to 6,000 Å. In accordance with one aspect of the invention, active regions are formed in the substrate between the isolation block and at least one of the gate electrode stacks.

Abstract: A transistor and a method of making the same are provided. The transistor includes a substrate and a gate dielectric layer positioned on the substrate that has first and second sidewall spacers. A gate electrode is positioned on the gate dielectric layer between the first and second sidewall spacers. A semiconductor layer is positioned on the substrate and adjacent the gate dielectric layer. First and second source/drain regions are provided wherein each of the first and second source/drain regions has a first portion positioned in the semiconductor layer and a second portion positioned in the substrate. Processing of the gate dielectric layer and the sidewall spacers is integrated.

Abstract: A semiconductor device having a reduced polysilicon gate electrode width and a process for manufacturing such a device is provided. Consistent with the present invention a semiconductor device is formed by forming an insulating film selective to oxide etchant over a substrate. At least one polysilicon block is formed over the insulating film. The polysilicon block is oxidized to grow an oxide layer on exposed surfaces of the polysilicon block and thereby reduce the width of the polysilicon block. The oxide layer is then removed to form a gate electrode with the remaining portion of the polysilicon block. In this manner, gate electrodes having widths smaller than the resolution of current etching techniques can be formed. In accordance with one aspect of the invention, the polysilicon gate electrode has a width less than about 0.15 microns. In accordance with another aspect, the insulating layer selective to oxide etchant is formed from a high permittivity material, such as a barium strontium titanate oxide.

Abstract: A semiconductor process in which a low temperature oxidation of a semiconductor substrate upper surface followed by an in situ deposition of polysilicon are used to create a thin oxide MOS structure. Preliminarily, the upper surface of a semiconductor substrate is cleaned, preferably with a standard RCA clean procedure. A gate dielectric layer is then formed on the upper surface of the substrate. A first polysilicon layer is then in situ deposited on the gate dielectric layer. An upper portion of the first polysilicon layer is then oxidized and the oxidized portion is thereafter removed from the upper surface of the first polysilicon layer. A second polysilicon layer is subsequently deposited upon the first polysilicon layer. Preferably, the formation of the gate dielectric on the semiconductor substrate upper surface comprises annealing the semiconductor substrate in an ambient comprising an inert species and O2.

Abstract: In insulated-gate, field effect transistor (IGFET) devices fabricated in integrated circuits, the scaling down of the dimensions of the devices has resulted in structures with dimensions are so small that reproducibility of parameters can become problematic. Specifically, the gate dielectric, typically silicon nitride, silicon oxide or silicon nitride, of a gate structure is nearing the point where the required thickness of the gate dielectric to provide the selected electric field in the channel region is implemented with a few to several atomic layers. In order to improve parameter reproducibility, a dielectric material, such TaO5 or a ferroelectric material, is used as a gate dielectric. TaO5 and the ferroelectric materials have a dielectric constant an order of magnitude higher than the material typically used in the past. Using these materials, the gate dielectric can be proportionately thicker, thereby improving the parameter reproducibility.

Abstract: In an integrated circuit, a pair of IGFET devices can be formed with reduced dimensions without requiring the use of higher resolution optical masks. A gate electrode is formed with a layer of silicon nitride and a photoresist layer formed thereon. The dimensions of the photoresist layer are reduced by a trim etch and the dimension of the nitride layer reduced by a nitride etch. After removing the photoresist layer, a silicon oxide layer is grown over the exposed gate electrode and substrate. The nitride layer is removed leaving a pattern in the silicon oxide layer. An anisotropic etch guided by the pattern in the silicon oxide layer divides the gate electrode into two portions with an aperture therebetween. By proper doping, a IGFET structure can be formed that has two IGFET devices having a shared source/drain region and occupying the same area on the surface of the substrate as a single IGFET device previously occupied.

Abstract: The present invention is directed to a semiconductor device having an improved structure for isolating transistors formed on a semiconductor substrate, and a method for making same. The device is comprised of a semiconductor device having first and second recesses formed in the substrate of the device. The inventive method disclosed herein comprises forming first and second recesses in the substrate of the device. The first width of the first recess is formed such that it is greater than the second width of the second recess, and the second depth of the second recess is formed such that it is greater than the first depth of the first recess.

Abstract: A transistor and a method of making the same are provided. The method includes the steps of forming a gate dielectric stack on the substrate that has a gate dielectric layer and forming first and second sidewall spacers adjacent the gate dielectric stack. A first portion of the gate dielectric stack is removed while a second portion thereof is left in place. First and second source/drain regions are formed in the substrate, and a conductor layer is formed over the first and second source/drain regions and on the second portion of the gate dielectric stack. The gate dielectric may be composed of a high dielectric constant material with a thin equivalent thickness of oxide. The method enables integrated processing of the gate electrode and source/drain metallization.

Abstract: An integrated circuit includes a plurality of transistors formed to include insulative punchthrough regions. Each of the plurality of transistors includes a channel formed upon a substrate, an insulative punchthrough region formed below the channel, a source formed upon the insulative punchthrough region residing adjacent a first end of the channel, a drain formed upon the insulative punchthrough region residing adjacent a second end of the channel, a gate oxide formed above the channel and a gate conductor formed above the gate oxide. Isolation regions may also be formed in the substrate that have an etch stop defination that was formed upon formation of the insulative punchthrough region. A voltage threshold region may be formed between the gate oxide and the channel and lightly doped regions may be formed adjacent the channel. The insulative punchthrough region may be and oxide layer formed within the substrate in an oxygen implant step that also formed the etch stop defination.

Abstract: An integrated circuit fabrication process is provided in which a gate electrode including a gate dielectric and a gate conductor is formed upon a semiconductor substrate. Preferably, the gate dielectric has a dielectric constant greater than the dielectric constant of silicon dioxide. In an embodiment, sidewall spacers are formed laterally adjacent opposed sidewall surfaces of the gate electrode. An interlevel dielectric is then formed above the semiconductor substrate and selectively removed from above active regions of the semiconductor substrate to form an opening. Source and drain implant areas are formed self-aligned with the opposed sidewall spacers. A metal silicide layer may be formed across upper surfaces of the gate conductor and source and drain areas, a second interlevel dielectric deposited in the opening, and contacts formed through the second interlevel dielectric to the metal silicide.

Abstract: The present invention is directed to a novel semiconductor device and a method for making same. As disclosed herein, a gate dielectric comprised of epitaxial metal oxide is positioned above a semiconducting substrate. A gate conductor comprised of an epitaxial conductive material is positioned above the gate dielectric. The method comprises forming a layer of an epitaxial metal oxide above a semiconducting substrate, forming a layer of epitaxial conductive material above the layer of epitaxial metal oxide, and forming a source/drain region.

Abstract: The present invention is directed to a method and apparatus for reducing the thickness of a process layer. The method comprises generating a relatively high velocity gas stream comprised of active ions that will react with the process layer, and moving the wafer relative to the nozzle to effect a reduction in the thickness of the process layer. The apparatus is comprised of a process chamber, means for securing a wafer in the chamber, a nozzle having an exit that is substantially the same width as the diameter of the wafer positioned in the chamber. The apparatus further comprises a means for moving the wafer relative to the nozzle.

Abstract: The present invention is directed to a new semiconductor device and a method for making same. The new semiconductor device is comprised of a gate barrier layer, a composite gate dielectric layer, a conductor layer, and at least one source/drain region formed in aemiconducting substrate. The method comprises forming the gate barrier layer, composite gate dielectric layer and conductor layer, patterning those layers, and forming at least one source/drain region in said semiconductor substrate. The composite gate dielectric layer is comprised of at least two different materials having different dielectric constants.

Abstract: An integrated circuit fabrication process is provided for forming a transistor in which the channel length is mandated by the width of a gate conductor formed upon a gate dielectric having a dielectric constant greater than about 3.8. The thickness of the gate dielectric may be made sufficiently large to serve as a mask during subsequent implantation of impurities into a substrate. The gate conductor and the gate dielectric are first patterned using lithography and an etch step. In one embodiment, a masking layer is then formed across a select portion of the gate conductor and an ensuing source region of the substrate. The uncovered portion of the gate conductor is etched to expose a region of the gate dielectric. A first implant of impurities is forwarded into regions of the substrate not covered by the masking layer to form an LDD area underneath the exposed region of the gate dielectric and a heavily doped drain region laterally adjacent the LDD area.

Abstract: The present disclosure relates to a chemical vapor deposition system including a chemical vapor deposition chamber having a wafer position at which a wafer can be placed during chemical wafer deposition processing, and a source of reactive gases for providing reactive gases to the chemical vapor deposition chamber. This system also includes a coherent radiation source for directing a beam of coherent radiation toward the wafer position, and a shield positioned between the coherent radiation source and the wafer position. This shield is adapted to distribute energy from the beam of coherent radiation across the wafer when the wafer is located at the wafer position.

Abstract: An apparatus for in-situ cleaning of polysilicon-coated quartz furnaces are presented. Traditionally, disassembling and reassembling the furnace is required to clean the quartz. This procedure requires approximately four days of down time which can be very costly for a company. In addition, cleaning the quartz requires large baths filled with a cleaning agent. These baths occupy a large amount of laboratory space and require a large amount of the cleaning agent. Cleaning the furnace in-situ eliminates the very time consuming procedure of assembling and disassembling the furnace and at the same time requires less laboratory space and less amount of cleaning agent. The polysilicon remover may be either a mixture of hydrofluoric and nitric acid or TMAH. TMAH is preferred because it less hazardous than hydrofluoric acid and compatible with more materials. The cleaning agent may be introduced into the furnace either from the built-in injectors or from additionally installed injectors.