Abstract: An integrated circuit fabrication process is provided for forming a transistor having an ultra short channel length. First and second masks are formed upon a conductive gate layer, wherein the second mask has a second lateral dimension less than a first lateral dimension of the first mask. The second mask is used to pattern a gate conductor from the conductive gate layer such that the gate conductor has an ultra narrow lateral dimension. Lightly doped drain impurity areas are formed self-aligned to sidewall surfaces of the gate conductor. Spacers are formed laterally adjacent the sidewall surfaces of the gate conductor, and source and drain impurity areas are formed self-aligned to sidewall surfaces of the spacers.

Abstract: A semiconductor device having an oxide layer formed by outgassing oxide from a showerhead and an apparatus and process for fabricating such a device is provided. A process for fabricating a semiconductor device, in accordance with one embodiment of the invention, includes placing a substrate in a chamber having an oxide source showerhead and outgassing oxide from the showerhead to form an oxide layer on the substrate. The oxide layer may be used, at least in part, as a gate dielectric for a transistor device and may have a thickness as thin as one or two molecules. The oxide source showerhead may, for example, be formed from a block of quartz, thereby providing a silicon oxide layer on the substrate.

Abstract: Fluorine bearing spacers on the sidewalls of gate electrodes of a semiconductor device are provided to suppress hot carrier injection in the semiconductor device. In accordance with one embodiment of the invention, a semiconductor device is formed by forming at least one gate electrode on a surface of a substrate and forming fluorine bearing spacers on the sidewalls of the gate electrode. The fluorine bearing spacers may, for example, be formed of an NF.sub.3 -doped glass material.

Abstract: A semiconductor device having a gate insulating tri-layer includes a substrate, a nitrogen-containing layer disposed on the substrate, a first dielectric layer disposed over the nitrogen containing layer, a second dielectric layer disposed over the first dielectric layer, and a gate electrode disposed over the second dielectric layer. One of the first and second dielectric layers is formed using an oxide having a dielectric constant ranging from 4 to 100 and the other of the first and second dielectric layers is formed using an oxide having a higher dielectric constant ranging from 10 to 10,000.

Abstract: A semiconductor device and manufacturing process in which a nitrogen bearing isolation region is formed. In one embodiment of the invention, a semiconductor device is formed by forming, in a substrate, one or more trenches each of which define an isolation region. In each trench, an insulating region is formed. In each trench over the insulating region, a nitrogen bearing region is formed. The nitrogen bearing region may, for example, be a nitride. A semiconductor device consistent with one embodiment of the invention includes a substrate having a plurality of active regions and one or more nitrogen bearing isolation regions separating the active regions. Each isolation region generally includes an insulating region adjacent the substrate and a nitrogen bearing region disposed over the insulating region and separated from the substrate by the oxide region. The nitrogen bearing region may, for example, be a nitride.

Abstract: The present invention is directed to am improved chemical mechanical polish etch stop for a trench isolation and a method for making same. The method comprises forming at least four process layers above a surface of a semiconducting substrate. The method further comprises patterning said plurality of process layers to define an opening exposing a portion of the surface of the substrate. A trench is formed in the substrate, and the trench and the opening are then filled with a dielectric material. The surface of the dielectric material and the surface of the top process layer are then planarized. The present inventive structure is comprised of at least four process layers positioned above a substrate, an opening formed in said plurality of layers, a trench formed in said substrate, and a dielectric material positioned in said opening and said.

Abstract: A semiconductor device is formed by forming a sacrificial plug over a substrate and forming active regions in the substrate adjacent the sacrificial plug. A film is then formed over portions of the substrate adjacent the sacrificial plug. The sacrificial plug is then selectively removed leaving an opening in the film, and a gate electrode is formed in the opening. The sacrificial plug can be formed from several materials including, for example, polysilicon and nitrogen-bearing species such as nitride. The gate electrode may, for example, be formed from temperature-sensitive metals such as copper since the gate electrode may be formed subsequent to high temperature steps of the fabrication, such as a source drain anneal, for example.

Abstract: A transistor and a method for making a transistor are described. Barrier species such as nitrogen may be introduced into a semiconductor substrate to form a barrier layer. A dielectric having a high dielectric constant, preferably a metal- and oxygen-bearing dielectric, may then be deposited upon the semiconductor substrate. The barrier layer preferably mitigates short channel effects and prevents dopant and/or metal atom migration into or out of the gate structure. The dielectric may be annealed in an oxygen-bearing atmosphere to passivate the dielectric material and to incorporate barrier species into the dielectric. Alternatively, the anneal may be performed in an inert atmosphere. Following deposition of a conductive gate material upon the dielectric, a gate conductor and gate dielectric may be patterned. Lightly doped drain impurity areas and/or source and drain impurity areas may then be formed in the semiconductor substrate.

Abstract: A memory device having a high performance stacked dielectric sandwiched between two polysilicon plates and method of fabrication thereof is provided. A memory device, in accordance with an embodiment, includes two polysilicon plates and a high permittivity dielectric stack disposed between the two polysilicon plates. The high permittivity dielectric stack includes a relatively high permittivity layer and two relatively low permittivity buffer layers. Each buffer layer is disposed between the relatively high permittivity layer and a respective one of the two polysilicon plates. The high permittivity layer may, for example, be a barium strontium titanate and the buffer layers may each include a layer of silicon nitride adjacent the respective polysilicon plate and a layer of titanium dioxide between the silicon nitride and the barium strontium titanate. The new high performance dielectric layer can, for example, increase the speed and reliability of the memory device as compared to conventional memory devices.

Abstract: Generally, the present invention relates to a semiconductor device having a dual gate electrode material and a process of fabricating such a device. Consistent with one embodiment of the invention, a semiconductor device is formed by forming a first gate electrode over the substrate and forming a second gate electrode from a different material than the first gate electrode over the substrate. For example, the first gate electrode may be formed from polysilicon and a second gate electrode may be formed from a metal such as aluminum, titanium, cobalt, or copper.

Abstract: A semiconductor process in which a silicon film is chemically vapor deposited upon a native oxide film as part of the gate oxide formation process. The invention contemplates a method of forming a thin gate dielectric semiconductor transistor. A semiconductor substrate which includes a native oxide film on an upper region of a silicon bulk is provided and a silicon film is deposited on the native oxide film. A first oxide film is then formed on a the native oxide film by thermally oxidizing a portion of the silicon film proximal to the native oxide film such that the thin gate dielectric comprises the native oxide film and the first oxide film. Thereafter, a conductive gate is formed on the thin gate dielectric and a pair of source/drain structures are formed within a pair of source/drain regions of the semiconductor substrate. The pair of source/drain structures are laterally displaced on either side of the channel region of the semiconductor substrate.

Abstract: The present invention relates to a process of forming a semiconductor device including forming a gallium and nitrogen bearing layer and forming at least one gate electrode over the gallium and nitrogen bearing barrier layer. The invention also includes a semiconductor device formed according to this process. In another embodiment, the invention includes a semiconductor device including a substrate, a gallium and nitrogen containing barrier layer disposed over the substrate, and at least one gate electrode disposed over the gallium and nitrogen bearing barrier layer.

Abstract: A semiconductor device having a gate insulating layer that includes a high permittivity layer between thin nitride layers. A first nitride layer formed on a silicon substrate to control unwanted oxidation of the substrate. A high permittivity layer is deposited on the first nitride layer, and a second nitride layer deposited on the permittivity layer. A gate electrode is formed on the second nitride layer. The second nitride layer prevents oxidation of the gate electrode from the high permittivity layer.

Abstract: A semiconductor process including forming a gate dielectric on a semiconductor substrate. First and second conductive gates are then formed on the gate dielectric. The conductive gates are aligned over respective channel regions of the substrate. The channel regions are laterally displaced between respective pairs of source/drain regions. A first interlevel dielectric is then deposited on the substrate and source/drain vias are then formed in the interlevel dielectric. The source/drain vias terminate on the pairs of source/drain regions. Thereafter, a source/drain impurity is introduced into the source/drain regions to form source/drain structures. A conductivity type of the source/drain structures is opposite a conductivity type of the field region. The first interlevel dielectric substantially prevents the source/drain impurity from entering the field region of the semiconductor substrate.

Abstract: The present invention is directed to a new semiconductor device and a method for making same. The semiconductor device is comprised of a gate dielectric layer, a conductor layer, and a metal oxide layer positioned between the gate dielectric layer and the conductor layer. The method comprises forming a gate dielectric layer, a conductor layer, and a metal oxide layer between the gate dielectric layer and the conductor layer.

Abstract: An integrated circuit and process for making the same is provided in which a gate electrode including a gate dielectric and a gate conductor is formed upon a semiconductor substrate. Preferably, the gate dielectric has a dielectric constant greater than the dielectric constant of silicon dioxide. In an embodiment, the gate dielectric is formed from a first compound material, and the gate conductor is formed from a second compound material different from the first compound material. Preferably, the gate dielectric is selectively etched such that a portion of the gate conductor extends beyond sidewall surfaces of the gate dielectric, forming a T-shaped gate electrode. In an embodiment, a first ion implantation is used to form lightly doped drain areas aligned with the gate dielectric sidewall surfaces using a large tilt angle implant. Source and drain implant areas are then formed self-aligned with the sidewalls of opposed sidewall spacers using a second ion implant.

Abstract: A semiconductor device fabrication process in which an oxynitride layer and a polysilicon layer are formed in the same reaction chamber is provided. In accordance with one embodiment of the invention, a semiconductor device is formed by forming, in a reaction chamber, an oxynitride layer on a surface of a substrate and forming, in the same reaction chamber, a polysilicon layer over the oxynitride layer. The oxynitride layer may be used to form a gate oxide and the polysilicon layer used to form a gate electrode.

Abstract: An integrated circuit fabrication process is provided for forming a transistor having an ultra short channel length. A mask is formed, from a material resistant to oxidation, upon a conductive gate layer and portions of the conductive gate layer are oxidized to form a gate conductor laterally disposed between a pair of oxide regions. As a result, the gate conductor has an ultra narrow lateral dimension. Source and drain impurity areas are formed self-aligned with sidewall surfaces of the oxide regions. In an embodiment, the oxide regions are removed and lightly doped drain regions are formed self-aligned with sidewall surfaces of the gate conductor. Following LDD formation, the mask is removed, spacers are formed laterally adjacent the gate conductor sidewall surfaces, and a metal silicide is formed upon upper surfaces of the gate conductor and the source and drain impurity areas.

Abstract: A method if provided for forming a diamond etch stop layer across a transistor to protect the source and drain junctions and the gate conductor of the transistor from being etched. The diamond may be CVD deposited from a hydrocarbon-bearing gas across the transistor. An interlevel dielectric comprising oxide is formed across the diamond etch stop layer. Contact openings may be etched through the oxide interlevel dielectric to the source and drain junctions and the gate conductor using a fluorine-bearing plasma. Advantageously, a high etch rate selectivity of oxide to diamond may be achieved using the fluorine-bearing plasma. As such, the plasma etch may be terminated well before significant portions of the diamond can be removed. Ti atoms may be implanted into regions of the diamond exposed by the contact openings and subsequently heated to render those regions of the diamond conductive.

Abstract: A semiconductor process in which an initial gate dielectric layer is formed on an upper surface of a semiconductor substrate. The initial gate dielectric layer is polished with a chemical mechanical polish to produce a finished gate dielectric layer. A thickness of the finished gate dielectric layer is less than a thickness of the initial gate dielectric layer and the thickness of the preferred finished gate dielectric layer is in the range of approximately 25 to 60 angstroms. In one embodiment, the initial gate dielectric layer is formed by thermally oxidizing the semiconductor substrate in an oxygen bearing ambient maintained at a temperature in the range of approximately 600.degree. C. to 900.degree. C. In an alternative embodiment, the formation of the initial gate dielectric layer is achieved by depositing an oxide.