Abstract: A semiconductor process in which oxygen is selectively implanted into isolation regions of a semiconductor substrate and subsequently annealed to form isolation structures within the isolation regions. Preferably, a semiconductor substrate is provided and a pad oxide layer is deposited on the semiconductor substrate. A barrier layer is then deposited on the pad oxide layer and a photoresist layer is formed over the barrier layer and patterned to form a photoresist mask. The photoresist mask is aligned over active regions of the semiconductor substrate. An oxygen bearing species is then introduced to an isolation region of the semiconductor substrate. The isolation region is laterally displaced between the active regions. The introducing of the oxygen bearing species into the isolation region results in the formation of an oxygenated region of the semiconductor substrate.

Abstract: A semiconductor device having a nitrogen enhanced high permittivity gate insulating layer and a process for manufacturing such a device is provided. Consistent with one embodiment, a high permittivity gate insulating layer is formed over a substrate using a nitrogen bearing gas. The gate insulating layer has a dielectric constant of at least 20. At least one gate electrode is formed over the high permittivity gate insulating layer. An optional nitride capping layer can be formed between the high permittivity gate insulating layer and the gate electrode. The nitrogen bearing gas may include one or more nitrogen bearing species, such as NO, NF.sub.3 or N2, for example. The use of nitrogen in the formation of a high permittivity gate insulating layer can, for example, reduce oxidation of the high permittivity layer and increase the ability to control the characteristics of the gate insulating layer.

Abstract: A semiconductor device having a gate electrode stack formed using a patterned oxide layer is disclosed. The device is formed by forming an oxide layer over a surface of a substrate and forming at least one opening in the oxide layer. A high permittivity plug (e.g., a BST plug) is formed in the lower portion of the opening. A conductive plug (e.g., a metal silicide plug) is formed in an upper portion of the opening over the high permittivity plug. Remaining portions of the oxide layer are then removed. The conductive plug and high permittivity plug may form a gate electrode and a gate insulating layer, respectively.

Abstract: A semiconductor device having a high performance gate electrode structure and a process of fabricating such a device. A semiconductor device in accordance with an embodiment of the invention is formed by forming a gate insulating layer is over a substrate. A diffusion barrier layer is formed over the gate insulating layer and a trench is formed in the diffusion barrier layer. In the trench, a metal gate electrode is formed. The diffusion barrier layer impedes diffusion of the metal gate electrode into the gate insulating layer during, for example, subsequent processing. The gate insulating layer, the barrier layer, and the gate electrode may, for example, be formed from cobalt niobate, tantalum silicon nitride, and copper, respectively. The copper gate electrode and cobalt gate insulating layer can, for example, increase the speed of the semiconductor device as compared to conventional transistors.

Abstract: A substantially in situ trench isolation process is provided. The process includes forming a trench regions between active regions in a semiconductor substrate. The semiconductor substrate may be covered with a protective oxide pad and/or nitride layer. In a single chamber, an oxide is thermally grown in the trench, the nitride layer is substantially stripped, and a fill dielectric is deposited in the trench and over the active and trench regions. The invention contemplates thermal growth, etch, and deposition processes to be performed serially in a single chamber without opening the chamber. The invention further contemplates modifying or adapting a conventional process chamber to all for the in situ processing of thermal growth, etch, and deposition processes. Alternatively, a specialized chamber may be provided.

Abstract: A semiconductor device having a cobalt niobate-cobalt silicide gate electrode structure is provided. A semiconductor device, consistent with one embodiment of the invention, is formed by forming a cobalt niobate gate insulating layer over the substrate and forming a cobalt silicide layer over the cobalt niobate layer. The cobalt silicide layer and cobalt niobate gate insulating layer may, for example, be selectively removed to form at least one cobalt silicide-cobalt niobate gate electrode structure. The cobalt niobate-cobalt silicide gate electrode structure can, for example, increase the operating speed of the device as compared to conventional transistors.

Abstract: Fluorine bearing spacers on the sidewalls of gate electrodes of a semiconductor device are provided to suppress hot carrier injection in the semiconductor device. In accordance with one embodiment of the invention, a semiconductor device is formed by forming at least one gate electrode on a surface of a substrate and forming fluorine bearing spacers on the sidewalls of the gate electrode. The fluorine bearing spacers may, for example, be formed of an NF.sub.3 -doped glass material.

Abstract: An integrated circuit fabrication process is provided for forming silicon dioxide in the vacancies of a gate dielectric comprising metal oxide. The gate dielectric has a relatively high dielectric constant to promote high capacitive coupling between two conductive layers separated by the gate dielectric. The gate dielectric may be used in, e.g., a MOS transistor device or an EEPROM memory cell. The silicon dioxide is formed within the gate dielectric by first incorporating silicon atoms within the gate dielectric using gas cluster ion beam implantation. Gas cluster ion beam implantation affords shallow implantation of the silicon atoms. The gate dielectric is then annealed in a diffusion furnace while being exposed to a steam- or oxygen-bearing ambient. As a result of being heated, Si atoms react with O atoms to form SiO.sub.2 which fills oxygen vacancies in the gate dielectric. Absent the oxygen vacancies, the gate dielectric is less likely to allow current to leak between the two conductive layers. The SiO.

Abstract: An in situ process is provided for isolating semiconductor devices according to a LOCOS process. The invention contemplates performing field oxide growth, nitride layer removal, sacrificial oxide growth and removal, and gate oxide growth all within a single chamber without removing the wafers from the chamber during processing. The invention is believed to result in increased yields and process throughput by reducing the exposure of the wafers to outer-chamber contaminants, thermal stress, and transportation damage, as well as reducing inter-chamber transportation time. The invention also contemplates an in situ processing chamber adapted for performing field oxide growth, nitride layer removal, sacrificial oxide growth and removal, and gate oxide growth as part of a LOCOS isolation process. The in situ processing chamber is adapted for thermal oxidation and etching processes to implement the LOCOS isolation structure.

Abstract: A semiconductor device having a fluorine-enhanced transistor with elevated active regions and process for fabricating such a device is provided. A semiconductor device, consistent with one embodiment of the invention, includes a substrate and at least one pair of elevated active regions disposed on the substrate. A fluorine-bearing barrier layer is disposed over the substrate between the elevated active regions. A high permittivity layer is disposed over the barrier layer and between the elevated active regions. Finally, a gate electrode is disposed over the high permittivity layer. In some embodiments, a thin insulating layer is disposed between the gate electrode and the high permittivity layer. The thin insulating layer and the fluorine-bearing barrier layer may, for example, both be formed of a topaz, while the high permittivity layer may, for example, be formed from a manganese oxide.

Abstract: A semiconductor wafer comprising a single crystalline lattice suitable for use in the manufacture of integrated circuits, namely computer chips and dies, wherein a diameter of the wafer is greater than approximately 150 millimeters and wherein the wafer includes a first hole extending through the wafer. The hole is adapted to facilitate handling of the wafer without directly contacting a surface of the wafer. The wafer preferably includes a primary flat and the first hole includes a flat side having a predetermined and known orientation with respect to the primary flat of the wafer. In one embodiment, the wafer further includes a guide hole formed near the first hole such that the center-points of the first hole and the guide hole are oriented with a predetermined and known orientation with respect to the primary flat of the wafer.

Abstract: A method is provided for forming a non-volatile memory cell in which the upper surface of the floating gate is polished to reduce surface irregularities, providing for the formation of a gate dielectric having a relatively high breakdown voltage thereon. According to an embodiment, a first gate dielectric is thermally grown upon a semiconductor substrate which later serves as the tunnel dielectric in the ensuing memory cell. A floating gate polysilicon is deposited across the first gate dielectric, followed by ion implantation of dopants and nitrogen therein. The upper surface of the floating gate polysilicon is then polished using, e.g., CMP. A second gate dielectric comprising high quality oxynitride may then be thermally grown across the polished surface of the floating gate polysilicon. Alternately, a ceramic having a relatively high dielectric constant may be formed across the floating gate polysilicon to serve as the second gate dielectric.

Abstract: A semiconductor process in which a low temperature oxidation of a semiconductor substrate upper surface followed by an in situ deposition of polysilicon are used to create a thin oxide MOS structure. Preliminarily, the upper surface of a semiconductor substrate is cleaned, preferably with a standard RCA clean procedure. A gate dielectric layer is then formed on the upper surface of the substrate. A first polysilicon layer is then in situ deposited on the gate dielectric layer. An upper portion of the first polysilicon layer is then oxidized and the oxidized portion is thereafter removed from the upper surface of the first polysilicon layer. A second polysilicon layer is subsequently deposited upon the first polysilicon layer. Preferably, the formation of the gate dielectric on the semiconductor substrate upper surface comprises annealing the semiconductor substrate in an ambient comprising an inert species and O.sub.2.

Abstract: A semiconductor process in which a silicon film is chemically vapor deposited upon a native oxide film as part of the gate oxide formation process. The invention contemplates a method of forming a thin gate dielectric semiconductor transistor. A semiconductor substrate which includes a native oxide film on an upper region of a silicon bulk is provided and a silicon film is deposited on the native oxide film. A first oxide film is then formed on a the native oxide film by thermally oxidizing a portion of the silicon film proximal to the native oxide film such that the thin gate dielectric comprises the native oxide film and the first oxide film. Thereafter, a conductive gate is formed on the thin gate dielectric and a pair of source/drain structures are formed within a pair of source/drain regions of the semiconductor substrate. The pair of source/drain structures are laterally displaced on either side of the channel region of the semiconductor substrate.

Abstract: A method is provided for forming nitride sidewall spacers self-aligned between opposed sidewall surfaces of a gate conductor and a sacrificial dielectric sidewall. In one embodiment, a transistor is formed by first CVD depositing a sacrificial across a semiconductor substrate. An opening is etched through the dielectric to the underlying substrate. A gate oxide is thermally grown across the region of the substrate exposed by the first opening. A polysilicon gate conductor is then formed within the opening upon the gate oxide. Portions of the gate conductor and the gate oxide are removed to expose selective regions of the substrate. In this manner, a pair of opposed sidewall surfaces are defined for the polysilicon gate conductor which are laterally spaced from respective first and second dielectrics. A LDD implant is forwarded into those exposed selective regions of the semiconductor substrate.

Abstract: A semiconductor device manufacturing method of forming an isolation region of a semiconductor device with high planarization is provided. A semiconductor device is formed by forming a mask over a portion of a semiconductor substrate, the mask defining an exposed portion of the substrate. A first oxide region is grown in the exposed portion of the substrate and a second oxide region is formed over the first oxide region to form a composite oxide region. The mask is removed while leaving the composite oxide region. Spacers may be formed on sidewalls of the mask and removed after growing the first oxide region. The composite oxide region may, for example, form a field oxide region.

Abstract: A method for in-situ cleaning of polysilicon-coated quartz furnaces are presented. Traditionally, disassembling and reassembling the furnace is required to clean the quartz. This procedure requires approximately four days of down time which can be very costly for a company. In addition, cleaning the quartz requires large baths filled with a cleaning agent. These baths occupy a large amount of laboratory space and require a large amount of the cleaning agent. Cleaning the furnace in-situ eliminates the very time consuming procedure of assembling and disassembling the furnace and at the same time requires less laboratory space and less amount of cleaning agent. The polysilicon remover may be either a mixture of hydrofluoric and nitric acid or TMAH. TMAH is preferred because it less hazardous than hydrofluoric acid and compatible with more materials. The cleaning agent may be introduced into the furnace either from the built-in injectors or from additionally installed injectors.

Abstract: A method for fabrication a gate dielectric in which an initial dielectric layer comprising a sacrificial portion and a permanent portion is formed on the semiconductor substrate. Thereafter the sacrificial portion is controllably removed with an etchback process. The gate dielectric is preferably comprised of oxynitride to reduce boron penetration from the conductive gate into the transistor channel region and the gate dielectric has a final thickness less than approximately 30 angstroms. The method includes providing a semiconductor substrate having channel region that is laterally displaced between a pair of source/drain regions. An upper surface of said semiconductor substrate is then cleaned and the semiconductor substrate is loaded into an oxidation chamber containing a first ambient maintained at a first temperature for a first duration to grow an initial dielectric layer over the channel region of said semiconductor substrate.

Abstract: A method of growing an oxide film in which the upper surface of a semiconductor substrate is cleaned and the semiconductor substrate is dipped into an acidic solution to remove any native oxide from the upper surface. The substrate is then directly transferred from the acidic solution to an oxidation chamber. The oxidation chamber initially contains an inert ambient maintained at a temperature of less than approximately 500.degree. C. The transfer is accomplished without substantially exposing the substrate to oxygen thereby preventing the formation of a native oxide film on the upper surface of the substrate. Thereafter, a fluorine terminated upper surface is formed on the semiconductor substrate. The temperature within the chamber is then ramped from the first temperature to a second or oxidizing temperature if approximately 700.degree. C. to 850.degree. C. The presence of the fluorine terminated upper surface substantially prevents oxidation of the semiconductor substrate during the temperature ramp.

Abstract: A semiconductor manufacturing process in which single crystal silicon substrate is immersed into an oxidation chamber maintained at a first temperature between 400.degree. and 700.degree. C. for a first duration. The oxidation chamber includes a first ambient gas of N.sub.2 or Argon. A second ambient gas is then introduced into the oxidation chamber. The second ambient gas includes a fluorine species to remove any residual oxide from the upper surface of the semiconductor substrate and to form a fluorine terminated upper surface. The ambient temperature within said oxidation chamber is then ramped to a second temperature in the range of approximately 600.degree. to 950.degree. C. A third ambient gas is introduced into said oxidation chamber to form a base oxide layer on the fluorine terminated upper surface of said semiconductor substrate. The third ambient gas includes oxygen and, preferably, the base oxide layer consists essentially of silicon and oxide.