Abstract: The present invention is directed to a method and apparatus for reducing the thickness of a process layer. The method comprises generating a relatively high velocity gas stream comprised of active ions that will react with the process layer, and moving the wafer relative to the nozzle to effect a reduction in the thickness of the process layer. The apparatus is comprised of a process chamber, means for securing a wafer in the chamber, a nozzle having an exit that is substantially the same width as the diameter of the wafer positioned in the chamber. The apparatus further comprises a means for moving the wafer relative to the nozzle.

Abstract: An integrated circuit and a method of making a transistor thereof are provided. The method includes the steps of forming a first stack on the substrate and a second stack on substrate in spaced-apart relation to the first stack, where the first stack has a first layer and first and second spacers adjacent to the first layer and the second stack has a second layer and third and fourth spacers adjacent to the second layer. A gate dielectric layer is formed on the substrate between the first and second stacks and a first conductor layer is formed on the gate dielectric layer. A first source/drain region is formed beneath the first conductor layer and a second source/drain region is formed beneath the second conductor layer. The first and second layers are removed and a first contact is formed on the first source/drain region and a second contact is formed on the second source/drain region.

Abstract: A method is presented for forming a transistor wherein a silicide layer is formed upon an impurity region of a semiconductor substrate. After forming the silicide layer, a gate structure is preferably formed upon an exposed portion of the semiconductor substrate; however, the silicide layer may be formed after forming the gate structure. In order to form the gate structure, a layer of sacrificial material is first formed above the semiconductor substrate. An opening is then patterned through the layer of sacrificial material such that a portion of the semiconductor substrate is exposed. The gate structure preferably includes a metal gate conductor and a metal oxide gate dielectric.

Abstract: A semiconductor device having a gate oxide layer formed by selective removal of the gate oxide layer and a process for manufacturing such a device is disclosed. A gate oxide layer is formed on a substrate. The gate oxide layer is selectively removed in a controlled ambient to reduce the thickness of the gate oxide layer. A gate electrode is disposed on the gate oxide layer. In accordance with one particular aspect of the process, the controlled ambient includes an NF.sub.3 bearing gas, which is flowed over the gate oxide layer to remove portions of the oxide layer.

Abstract: A semiconductor device having a nitrogen-bearing oxide gate insulating layer and methods of manufacture thereof are disclosed. A semiconductor device is formed by selecting a nitrogen-bearing species capable of providing a desired depth-distribution of nitrogen when an oxide layer is formed using the nitrogen-bearing species. The oxide layer is formed over a substrate, the oxide layer having the desired depth-distribution of nitrogen. A part of the oxide layer is selectively removed, giving the oxide layer a resultant depth-distribution of nitrogen. In accordance with another aspect of the process, a semiconductor device is formed by forming, in a reaction chamber, an oxide layer including nitrogen-bearing species on a substrate. A part of the oxide layer is selectively removed in the same reaction chamber.

Abstract: A method of making a semiconductor device includes forming gate electrode over a substrate and a protective layer over the gate electrode. A portion of the protective layer is selectively removed to expose a peripheral region of the gate electrode. A remainder of the protective layer remains disposed over a central region of the gate electrode. An upper portion of the peripheral region of the gate electrode is then removed typically leaving an underlying portion. Often, a dopant material is implanted into the substrate adjacent to and beneath the underlying portion to simultaneously form lightly-doped and heavily-doped regions beneath and adjacent to the underlying portion, respectively. In addition, all or part of the underlying portion may be oxidized to provide a gate electrode with reduced width.

Abstract: An integrated circuit fabrication process is provided for incorporating barrier atoms, preferably N atoms, within a gate dielectric/silicon-based substrate interfacial region using gas cluster ion beam implantation. Gas cluster ion beam implantation involves supercooling a gas to form clusters of atoms from the molecules in the gas. Those clusters of atoms are then ionized and accelerated to a target. Upon striking the target, the clusters of atoms break up into individual atoms. The energy of the ionized cluster is uniformly distributed to the individual atoms. As such, the atoms have a relatively low energy, and thus may be implanted to a shallow depth of less than 100 .ANG.. Barrier atoms positioned within a gate dielectric/substrate interfacial region serve to inhibit the diffusion of metal atoms and impurities from an overlying gate conductor into the substrate. Furthermore, the barrier layer provides protection against hot carrier injection into and entrapment within the gate dielectric.

Abstract: The present invention is directed to a new semiconductor device and a method for making same. The semiconductor device is comprised of a gate dielectric layer, a conductor layer, and a metal oxide layer positioned between the gate dielectric layer and the conductor layer. The method comprises forming a gate dielectric layer, a conductor layer, and a metal oxide layer between the gate dielectric layer and the conductor layer.

Abstract: The present invention is directed to a new semiconductor device and a method for making same. The new semiconductor device is comprised of a gate barrier layer, a composite gate dielectric layer, a conductor layer, and at least one source/drain region formed in a semiconducting substrate. The method comprises forming the gate barrier layer, composite gate dielectric layer and conductor layer, patterning those layers, and forming at least one source/drain region in said semiconductor substrate. The composite gate dielectric layer is comprised of at least two different materials having different dielectric constants.

Abstract: A transistor and a method of making the same are provided. The transistor includes a substrate that has an upper surface and a gate dielectric layer positioned on the substrate that has a first quantity of nitrogen therein. A gate electrode is positioned on the gate dielectric layer. First and second source/drain regions are positioned in the substrate and laterally separated to define a channel region beneath the gate dielectric layer. The gate dielectric layer may be composed of a high K material with a thin equivalent thickness of oxide, such as TiO.sub.2, Ta.sub.2 O.sub.5, CrO.sub.2 or SrO.sub.2. The nitrogen suppresses later oxide formation which may otherwise increase the equivalent thickness of oxide of the gate dielectric layer. Nitrogen may also be incorporated into the substrate and the gate electrode.

Abstract: A method is provided for forming nitride sidewall spacers self-aligned between opposed sidewall surfaces of a gate conductor and a sacrificial dielectric sidewall. In one embodiment, a transistor is formed by first CVD depositing a sacrificial across a semiconductor substrate. An opening is etched through the dielectric to the underlying substrate. A gate oxide is thermally grown across the region of the substrate exposed by the first opening. A polysilicon gate conductor is then formed within the opening upon the gate oxide. Portions of the gate conductor and the gate oxide are removed to expose selective regions of the substrate. In this manner, a pair of opposed sidewall surfaces are defined for the polysilicon gate conductor which are laterally spaced from respective first and second dielectrics. A LDD implant is forwarded into those exposed selective regions of the semiconductor substrate.

Abstract: A method of utilizing a non-epitaxial starting material in a CMOS semiconductor fabrication process. A bulk impurity distribution is non-selectively introduced into the starting material. The starting material includes a substantially uniformly doped wafer having a sheet resistivity in the range of approximately 5 to 25 .OMEGA.-cm. An upper boundary of the bulk impurity distribution is displaced below an upper surface of the wafer by a first depth. A peak impurity concentration of the bulk impurity distribution is greater than approximately 1.times.10.sup.19 atom/cm.sup.3. Thereafter, a barrier impurity distribution is introduced into the wafer. A peak concentration of the barrier impurity distribution is displaced below the upper surface of the wafer by a second depth. The first depth is greater than the second depth such that the barrier impurity distribution may substantially prevent the bulk impurity distribution from migrating into the upper region of the wafer.

Abstract: Apparatus and method for depositing fluids on both sides of a semiconductor wafer that has a central opening are provided. In one aspect, the apparatus includes a mandrel for holding the wafer and a motor coupled to the mandrel and that is operable to rotate the mandrel. The apparatus also includes means for dispensing a first volume of fluid on the semiconductor wafer and a second volume of fluid on the semiconductor wafer. According to the method, a semiconductor wafer is coupled to a rotatable mandrel. The mandrel is rotated to spin the semiconductor wafer and a semiconductor processing fluid is sprayed on the first and second sides of the semiconductor wafer.

Abstract: A transistor and a method of making the same are provided. The method includes the step of forming a gate dielectric layer on the substrate where the gate dielectric layer is composed of an aluminum oxide containing material. A gate electrode is formed on the gate dielectric layer and first and second source/drain regions are formed in the substrate laterally separated to define a channel region beneath the gate electrode. The aluminum oxide containing material may be, for example, Al.sub.2 O.sub.3. Aluminum oxide provides for a gate dielectric with a thin equivalent thickness of oxide in a potentially single crystal form.

Abstract: A process for manufacturing a high performance transistor with self-aligned dopant profile. The process involves forming a source/drain mask pattern on a substrate. With a first implant material, unmasked portions of the substrate are doped to form source/drain regions of the substrate. The source-drain mask is removed and an oxidation layer is grown, where portions of the oxidation layer formed from doped regions of the substrate have heights that are greater than heights of portions of the oxidation layer formed from un-doped regions of the substrate, thereby forming a gate mask. The doped portions of the substrate are self-aligned with gate regions of the substrate. The gate regions are doped, and gate electrodes are formed. The gate mask is removed to expose source/drain regions of the substrate for further fabrication.

Abstract: Apparatus and method for polishing one or both sides of a semiconductor wafer that has a central opening are provided. In one aspect, the apparatus includes a mandrel for holding the wafer and a motor coupled to the mandrel that is operable to rotate the mandrel. A first polisher assembly is provide that has a first polish pad for polishing the first side of the wafer and a second polish pad for polishing the second side of the wafer, and first means for moving the first and second polish pads into and out of engagement with the first and second sides of the wafer. According to the method, a semiconductor wafer is coupled to a rotatable mandrel and a polishing mixture is dispensed on one or both of the sides of the semiconductor wafer. A first polish pad is brought into contact with the first side of the semiconductor wafer and a second polish pad is brought into contact with the second side of the semiconductor wafer such that the first and second polish pads are positioned in opposition.

Abstract: A process for forming a semiconductor device using a conductive etch stop. The process includes the steps of fabricating a wafer structure up to a first level oxide deposition. A conductive etch stop is deposited over the first level oxide deposition, and selected portions of the conductive etch stop are removed. An inter-level oxide layer is deposited on the conductive etch stop, and selected portions of the inter-level oxide deposition are etched up to the conductive etch stop. The conductive etch stop may be either removed from the semiconductor or left as a conductor.

Abstract: A process for reducing dimensions of circuit elements in a semiconductor device. The process reduces feature sizes by using an intermediate etchable mask layer between a photo-resistive mask and a layer to be etched. The etchable mask layer below the photo-resistive mask is etched and portions remain which undercut the pattern on the photo-resistive mask. After removing the photo-resistive mask, the remaining mask portions are then used to mask the layer to be etched. By undercutting the photo-resistive mask, the mask portions form a pattern having features with widths that are less than widths of features in the photo-resistive mask. The layer to be etched can then be etched to provide circuit elements with reduced dimensions.

Abstract: A semiconductor wafer comprising a single crystalline lattice suitable for use in the manufacture of integrated circuits, namely computer chips and dies, wherein a diameter of the wafer is greater than approximately 150 millimeters and wherein the wafer includes a first hole extending through the wafer. The hole is adapted to facilitate handling of the wafer without directly contacting a surface of the wafer. The wafer preferably includes a primary flat and the first hole includes a flat side having a predetermined and known orientation with respect to the primary flat of the wafer. In one embodiment, the wafer further includes a guide hole formed near the first hole such that the center-points of the first hole and the guide hole are oriented with a predetermined and known orientation with respect to the primary flat of the wafer.

Abstract: A semiconductor device having a cobalt niobate-cobalt silicide gate electrode structure is provided. A semiconductor device, consistent with one embodiment of the invention, is formed by forming a cobalt niobate gate insulating layer over the substrate and forming a cobalt silicide layer over the cobalt niobate layer. The cobalt silicide layer and cobalt niobate gate insulating layer may, for example, be selectively removed to form at least one cobalt silicide-cobalt niobate gate electrode structure. The cobalt niobate-cobalt silicide gate electrode structure can, for example, increase the operating speed of the device as compared to conventional transistors.