Patents by Inventor Mark Doczy

Mark Doczy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11462678
    Abstract: A pSTTM device includes a first electrode and a second electrode, a free magnet between the first electrode and the second electrode, a fixed magnet between the first electrode and the second electrode, a tunnel barrier between the free magnet and the fixed magnet, a coupling layer between the free magnet and the first electrode, where the coupling layer comprises a metal and oxygen and a follower between the coupling layer and the first electrode, wherein the follower comprises a magnetic skyrmion. The skyrmion follower may be either magnetically and electrically coupled to the free magnet to form a coupled system of switching magnetic layers. In an embodiment, the skyrmion follower has a weaker magnetic anisotropy than an anisotropy of the free magnet.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: October 4, 2022
    Assignee: Intel Corporation
    Inventors: Kevin O'Brien, Kaan Oguz, Charles Kuo, Mark Doczy, Noriyuki Sato
  • Patent number: 11437567
    Abstract: An apparatus comprises a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers, the tunnel barrier directly contacting a first side of the free layer, a capping layer contacting the second side of the free magnetic layer and boron absorption layer positioned a fixed distance above the capping layer.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: September 6, 2022
    Assignee: Intel Corporation
    Inventors: Justin Brockman, Christopher Wiegand, MD Tofizur Rahman, Daniel Ouelette, Angeline Smith, Juan Alzate Vinasco, Charles Kuo, Mark Doczy, Kaan Oguz, Kevin O'Brien, Brian Doyle, Oleg Golonzka, Tahir Ghani
  • Patent number: 11430943
    Abstract: A magnetic tunneling junction (MTJ) memory device including a free and fixed (reference) magnet between first and second electrodes, and a synthetic antiferromagnet structure (SAF) structure between the fixed magnet and one of the electrodes. The SAF structure includes a magnetic skyrmion. Two magnetic skyrmions within a SAF structure may have opposing polarity. A SAF structure may further include a coupling layer between two magnetic layers, as well as interface layers separated from the coupling layer by one of the magnetic layers. The coupling layer may have a spin-orbit coupling effect on the magnetic layers that is of a sign opposite that of the interface layers, for example to promote formation of the magnetic skyrmions.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: August 30, 2022
    Assignee: Intel Corporation
    Inventors: Kevin O'Brien, Kaan Oguz, Noriyuki Sato, Charles Kuo, Mark Doczy
  • Patent number: 11386951
    Abstract: A MTJ device includes a free (storage) magnet and fixed (reference) magnet between first and second electrodes, and a programmable booster between the free magnet and one of the electrodes. The booster has a magnetic material layer. The booster may further have an interface layer that supports the formation of a skyrmion spin texture, or a stable ferromagnetic domain, within the magnetic material layer. A programming current between two circuit nodes may be employed to set a position of the skyrmion or magnetic domain within the magnetic material layer to be more proximal to, or more distal from, the free magnet. The position of the skyrmion or magnetic domain to the MTJ may modulate TMR ratio of the MTJ device. The TMR ratio modulation may be employed to discern more than two states of the MTJ device. Such a multi-level device may, for example, be employed to store 2 bits/cell.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: July 12, 2022
    Assignee: Intel Corporation
    Inventors: Kevin O'Brien, Brian Doyle, Kaan Oguz, Noriyuki Sato, Charles Kuo, Mark Doczy
  • Patent number: 11348970
    Abstract: A spin orbit torque (SOT) memory device includes an SOT electrode on an upper end of an MTJ device. The MTJ device includes a free magnet, a fixed magnet and a tunnel barrier between the free magnet and the fixed magnet and is coupled with a conductive interconnect at a lower end of the MTJ device. The SOT electrode has a footprint that is substantially the same as a footprint of the MTJ device. The SOT device includes a first contact and a second contact on an upper surface of the SOT electrode. The first contact and the second contact are laterally spaced apart by a distance that is no greater than a length of the MTJ device.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: May 31, 2022
    Assignee: Intel Corporation
    Inventors: Kevin O'Brien, Benjamin Buford, Kaan Oguz, Noriyuki Sato, Charles Kuo, Mark Doczy
  • Patent number: 11257613
    Abstract: A perpendicular spin orbit torque (SOT) memory device includes an electrode having a spin orbit torque material, where the SOT material includes iridium and manganese and a perpendicular magnetic tunnel junction (pMTJ) device on a portion of the electrode. The pMTJ device includes a free magnet structure electrode, a fixed layer and a tunnel barrier between the free layer and the fixed layer and a SAF structure above the fixed layer. The Ir—Mn SOT material and the free magnet have an in-plane magnetic exchange bias.
    Type: Grant
    Filed: March 31, 2018
    Date of Patent: February 22, 2022
    Assignee: Intel Corporation
    Inventors: Kaan Oguz, Tanay Gosavi, Sasikanth Manipatruni, Charles Kuo, Mark Doczy, Kevin O'Brien
  • Patent number: 11227644
    Abstract: A spin orbit torque (SOT) memory device includes a MTJ device on a SOT electrode, where a first portion of the SOT electrode extends beyond a sidewall of the MTJ by a first length that is no greater than a height of the MTJ, and where a second portion of the first electrode extends from the sidewall and under the MTJ by a second length that is no greater than a width of the MTJ. The MTJ device includes a free magnet, a fixed magnet and a tunnel barrier between the free magnet and the fixed magnet.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: January 18, 2022
    Assignee: Intel Corporation
    Inventors: Kevin O'Brien, Noriyuki Sato, Kaan Oguz, Mark Doczy, Charles Kuo
  • Patent number: 10964886
    Abstract: The present disclosure relates to the fabrication of spin transfer torque memory devices, wherein a magnetic tunnel junction of the spin transfer torque memory device is formed with Heusler alloys as the fixed and free magnetic layers and a tunnel barrier layer disposed between and abutting the fixed Heusler magnetic layer and the free Heusler magnetic layer, wherein the tunnel barrier layer is lattice matched to the free Heusler magnetic layer. In one embodiment, the tunnel barrier layer may be a strontium titanate layer.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: Brian Doyle, Kaan Oguz, Satyarth Suri, Kevin O'Brien, Mark Doczy, Charles Kuo
  • Publication number: 20210013397
    Abstract: A pSTTM device includes a first electrode and a second electrode, a free magnet between the first electrode and the second electrode, a fixed magnet between the first electrode and the second electrode, a tunnel barrier between the free magnet and the fixed magnet, a coupling layer between the free magnet and the first electrode, where the coupling layer comprises a metal and oxygen and a follower between the coupling layer and the first electrode, wherein the follower comprises a magnetic skyrmion. The skyrmion follower may be either magnetically and electrically coupled to the free magnet to form a coupled system of switching magnetic layers. In an embodiment, the skyrmion follower has a weaker magnetic anisotropy than an anisotropy of the free magnet.
    Type: Application
    Filed: March 9, 2018
    Publication date: January 14, 2021
    Applicant: Intel Corporation
    Inventors: Kevin O'Brien, Kaan Oguz, Charles Kuo, Mark Doczy, Noriyuki Sato
  • Publication number: 20200006628
    Abstract: A magnetic tunneling junction (MTJ) memory device including a free and fixed (reference) magnet between first and second electrodes, and a synthetic antiferromagnet structure (SAF) structure between the fixed magnet and one of the electrodes. The SAF structure includes a magnetic skyrmion. Two magnetic skyrmions within a SAF structure may have opposing polarity. A SAF structure may further include a coupling layer between two magnetic layers, as well as interface layers separated from the coupling layer by one of the magnetic layers. The coupling layer may have a spin-orbit coupling effect on the magnetic layers that is of a sign opposite that of the interface layers, for example to promote formation of the magnetic skyrmions.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Inventors: Kevin O'Brien, Kaan Oguz, Noriyuki Sato, Charles Kuo, Mark Doczy
  • Publication number: 20200005861
    Abstract: A MTJ device includes a free (storage) magnet and fixed (reference) magnet between first and second electrodes, and a programmable booster between the free magnet and one of the electrodes. The booster comprises a magnetic material layer. The booster may further comprise an interface layer that supports the formation of a skyrmion spin texture, or a stable ferromagnetic domain, within the magnetic material layer. A programming current between two circuit nodes may be employed to set a position of the skyrmion or magnetic domain within the magnetic material layer to be more proximal to, or more distal from, the free magnet. The position of the skyrmion or magnetic domain to the MTJ may modulate TMR ratio of the MTJ device. The TMR ratio modulation may be employed to discern more than two states of the MTJ device. Such a multi-level device may, for example, be employed to store 2 bits/cell.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Inventors: Kevin O'Brien, Brian Doyle, Kaan Oguz, Noriyuki Sato, Charles Kuo, Mark Doczy
  • Publication number: 20190326353
    Abstract: A spin orbit torque (SOT) memory device includes an SOT electrode on an upper end of an MTJ device. The MTJ device includes a free magnet, a fixed magnet and a tunnel barrier between the free magnet and the fixed magnet and is coupled with a conductive interconnect at a lower end of the MTJ device. The SOT electrode has a footprint that is substantially the same as a footprint of the MTJ device. The SOT device includes a first contact and a second contact on an upper surface of the SOT electrode. The first contact and the second contact are laterally spaced apart by a distance that is no greater than a length of the MTJ device.
    Type: Application
    Filed: April 23, 2018
    Publication date: October 24, 2019
    Applicant: Intel Corporation
    Inventors: Kevin O'Brien, Benjamin Buford, Kaan Oguz, Noriyuki Sato, Charles Kuo, Mark Doczy
  • Publication number: 20190304524
    Abstract: A perpendicular spin orbit torque (SOT) memory device includes an electrode having a spin orbit torque material and a perpendicular magnetic tunnel junction (pMTJ) device on a portion of the electrode. The pMTJ device includes a free magnet structure electrode, where the free magnet structure includes a free magnet that is dipole coupled with a magnetic stability enhancement layer. The pMTJ device further includes a fixed layer and a tunnel barrier between the free layer and the fixed layer.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 3, 2019
    Inventors: Kaan Oguz, Charles Kuo, Mark Doczy, Kevin O'Brien
  • Publication number: 20190304653
    Abstract: A perpendicular spin orbit torque (SOT) memory device includes an electrode having a spin orbit torque material, where the SOT material includes iridium and manganese and a perpendicular magnetic tunnel junction (pMTJ) device on a portion of the electrode. The pMTJ device includes a free magnet structure electrode, a fixed layer and a tunnel barrier between the free layer and the fixed layer and a SAF structure above the fixed layer. The Ir—Mn SOT material and the free magnet have an in-plane magnetic exchange bias.
    Type: Application
    Filed: March 31, 2018
    Publication date: October 3, 2019
    Inventors: Kaan Oguz, Tanay Gosavi, Sasikanth Manipatruni, Charles Kuo, Mark Doczy, Kevin O'Brien
  • Publication number: 20190304523
    Abstract: A spin orbit torque (SOT) memory device includes a MTJ device on a SOT electrode, where a first portion of the SOT electrode extends beyond a sidewall of the MTJ by a first length that is no greater than a height of the MTJ, and where a second portion of the first electrode extends from the sidewall and under the MTJ by a second length that is no greater than a width of the MTJ. The MTJ device includes a free magnet, a fixed magnet and a tunnel barrier between the free magnet and the fixed magnet.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 3, 2019
    Applicant: Intel Corporation
    Inventors: Kevin O'Brien, Noriyuki Sato, Kaan Oguz, Mark Doczy, Charles Kuo
  • Publication number: 20190280188
    Abstract: An apparatus comprises a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers, the tunnel barrier directly contacting a first side of the free layer, a capping layer contacting the second side of the free magnetic layer and boron absorption layer positioned a fixed distance above the capping layer.
    Type: Application
    Filed: December 28, 2016
    Publication date: September 12, 2019
    Inventors: Justin BROCKMAN, Christopher WIEGAND, MD Tofizur RAHMAN, Daniel OUELETTE, Angeline SMITH, Juan ALZATE VINASCO, Charles KUO, Mark DOCZY, Kaan OGUZ, Kevin O'BRIEN, Brian DOYLE, Oleg GOLONZKA, Tahir GHANI
  • Publication number: 20190189913
    Abstract: The present disclosure relates to the fabrication of spin transfer torque memory devices, wherein a magnetic tunnel junction of the spin transfer torque memory device is formed with Heusler alloys as the fixed and free magnetic layers and a tunnel barrier layer disposed between and abutting the fixed Heusler magnetic layer and the free Heusler magnetic layer, wherein the tunnel barrier layer is lattice matched to the free Heusler magnetic layer. In one embodiment, the tunnel barrier layer may be a strontium titanate layer.
    Type: Application
    Filed: September 27, 2016
    Publication date: June 20, 2019
    Applicant: Intel Corporation
    Inventors: Brian Doyle, Kaan Oguz, Satyarth Suri, Kevin O'Brien, Mark Doczy, Charles Kuo
  • Patent number: 8319287
    Abstract: Described herein are metal gate electrode stacks including a low resistance metal cap in contact with a metal carbonitride diffusion barrier layer, wherein the metal carbonitride diffusion barrier layer is tuned to a particular work function to also serve as a work function metal for a pMOS transistor. In an embodiment, the work function-tuned metal carbonitride diffusion barrier prohibits a low resistance metal cap layer of the gate electrode stack from migrating into the MOS junction. In a further embodiment of the present invention, the work function of the metal carbonitride barrier film is modulated to be p-type with a pre-selected work function by altering a nitrogen concentration in the film.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: November 27, 2012
    Assignee: Intel Corporation
    Inventors: Adrien R. Lavoie, Valery M. Dubin, John J. Plombon, Juan E. Dominguez, Harsono S. Simka, Joseph H. Han, Mark Doczy
  • Patent number: 8013401
    Abstract: A method for carrying out a replacement metal gate process comprises providing a transistor in a reactor, wherein the transistor includes a gate stack, removing at least a portion of the gate stack to expose a surface of a barrier layer, causing a temperature of the reactor be less than or equal to 150° C., introducing methylpyrrolidine:alane (MPA) proximate to the surface of the barrier layer, and carrying out a CVD process to deposit aluminum metal on the barrier layer using a bottom-up deposition mechanism.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: September 6, 2011
    Assignee: Intel Corporation
    Inventors: Adrien R. Lavoie, Mark Doczy
  • Patent number: 7936025
    Abstract: Described is a CMOS transistor structure with a multi-layered gate electrode structure and a method of fabrication. The gate electrode structure has a three-layered metallic gate electrode and a polysilicon layer. The first metallic layer acts as a barrier to prevent the second metallic layer from reacting with an underlying dielectric. The second metallic layer acts to set the work function of the gate electrode structure. The third metallic layer acts as a barrier to prevent the second metallic layer from reacting with the polysilicon layer.
    Type: Grant
    Filed: September 20, 2005
    Date of Patent: May 3, 2011
    Assignee: Intel Corporation
    Inventors: Robert Chau, Mark Doczy, Brian Doyle, Jack Kavalieros