Abstract: A transistor comprising a gate electrode formed on a gate dielectric layer formed on a substrate. A pair of source/drain regions are formed in the substrate on opposite sides of the laterally opposite sidewalls of the gate electrode. The gate electrode has a central portion formed on the gate dielectric layer and over the substrate region between the source and drain regions and a pair sidewall portions which overlap a portion of the source/drain regions wherein the central portion has a first work function and said pair of sidewall portions has a second work function, wherein the second work function is different than the first work function.

Abstract: A method for fabricating a three-dimensional transistor is described. Atomic Layer Deposition of nickel, in one embodiment, is used to form a uniform silicide on all epitaxially grown source and drain regions, including those facing downwardly.

Abstract: A transistor comprising a semiconductor including a source, a drain, and a channel interposed between the source and the drain; a first dielectric layer having a first thickness, the first dielectric layer being positioned on the channel; a second dielectric layer having a second thickness, the second dielectric layer being positioned on the first dielectric layer; and a gate electrode on the second dielectric layer, wherein the transistor gate is made of a mid-gap metal. A process comprising depositing a first dielectric layer on at least one surface of a semiconductor layer; depositing a second dielectric layer on the first dielectric layer; depositing a layer of mid-gap metal on the second dielectric layer; and patterning and etching the first dielectric layer, the second dielectric layer and the layer of mid-gap metal to create a gate electrode separated from the substrate by a first dielectric and a second dielectric. Other embodiments are disclosed and claimed.

Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.

Abstract: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer and reduced oxidation of a substrate beneath the high-k gate dielectric layer. An oxygen-scavenging spacer layer on side walls of the high-k gate dielectric layer and metal gate may reduce such oxidation during high temperature processes.

Abstract: Some embodiments of the present invention include apparatuses and methods relating to nonvolatile memory transistors.

Abstract: A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.

Abstract: A Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region.

Abstract: Embodiments of a transition metal alloy having an n-type or p-type work function that does not significantly shift at elevated temperature. The disclosed transition metal alloys may be used as, or form a part of, the gate electrode in a transistor. Methods of forming a gate electrode using these transition metal alloys are also disclosed.

Abstract: A process depositing a carbon- and transition metal-containing thin film on a substrate involves placing a substrate within a reaction space and sequentially pulsing into the reaction space a transition metal chemical and an organometallic chemical. Following each chemical pulse, the reaction space is purged, and the pulse and purge sequence is repeated until a desired film thickness is obtained. A preferred deposition process uses atomic layer deposition techniques and may result in an electrically conductive thin carbide film having uniform thickness over a large substrate area and excellent adhesion and step coverage properties.

Abstract: A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.

Abstract: A method utilizing a common gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby.

Abstract: A method for cleaning optics in a chamber. The method can include introducing a first etchant into a chamber that encloses an optical component and a source of electromagnetic radiation that is suitable for lithography, ionizing the first etchant, and removing debris from a surface of the optical component.

Abstract: Embodiments of a transition metal alloy having an n-type or p-type work function that does not significantly shift at elevated temperature. The disclosed transition metal alloys may be used as, or form a part of, the gate electrode in a transistor. Methods of forming a gate electrode using these transition metal alloys are also disclosed.

Abstract: Complementary metal oxide semiconductor metal gate transistors may be formed by depositing a metal layer in trenches formerly inhabited by patterned gate structures. The patterned gate structures may have been formed of polysilicon in one embodiment. The trenches may be filled with metal by surface activating using a catalytic metal, followed by electroless deposition of a seed layer followed by superconformal filling bottom up.

Abstract: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer, source/drain extensions a distance beneath the metal gate, and lateral undercuts in the sides of the metal gate.

Abstract: In a metal gate replacement process, a cup-shaped gate metal oxide dielectric may have vertical portions that may be exposed to a reduction reaction. As a result of the reduction reaction, the vertical portions may be converted to metal, which adds to the existing gate electrode. In some cases, removing the vertical dielectric portions reduces fringe capacitance and may also advantageously slightly increased underdiffusion without adding heat, in some embodiments.

Abstract: A sacrificial gate structure, including nitride and fill layers, may be replaced with a metal gate electrode. The metal gate electrode may again be covered with a nitride layer covered by a fill layer. The replacement of the nitride and fill layers may reintroduce strain and provide an etch stop.

Abstract: In a metal gate replacement process, a cup-shaped gate metal oxide dielectric may have a vertical portion that may be exposed to a silicon ion implantation. As a result of the implantation, the dielectric constant of a vertical portion may be reduced, reducing fringe capacitance.

Abstract: A method for making a semiconductor device is described. That method includes forming on a substrate a dielectric layer that has a dielectric constant that is greater than the dielectric constant of silicon dioxide. The dielectric layer is modified so that it will be compatible with a gate electrode to be formed on the dielectric layer, and then a gate electrode is formed on the dielectric layer.