Patents by Inventor Mark Doczy

Mark Doczy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Block contact architectures for nanoscale channel transistors
    Publication number: 20070001219
    Abstract: A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 4, 2007
    Inventors: Marko Radosavljevic, Amlan Majumdar, Brian Doyle, Jack Kavalieros, Mark Doczy, Justin Brask, Uday Shah, Suman Datta, Robert Chau
  • Strained field effect transistors
    Publication number: 20060292776
    Abstract: An NMOS transistor may be formed with a biaxially strained silicon upper layer having a thickness of greater than 500 Angstroms. The resulting NMOS transistor may have good performance and may exhibit reduced self-heating. A PMOS transistor may be formed with both a biaxially and uniaxially strained silicon germanium layer. A source substrate bias applied to both NMOS and PMOS transistors can enhance their performance.
    Type: Application
    Filed: June 27, 2005
    Publication date: December 28, 2006
    Inventors: Been-Yih Jin, Robert Chau, Suman Datta, Brian Doyle, Jack Kavalieros, Justin Brask, Mark Doczy, Matthew Metz, Markus Kuhn, Marko Radosavlievic, M. Shaheed, Patrick Keys
  • Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate
    Publication number: 20060286729
    Abstract: A complementary metal oxide semiconductor integrated circuit may be formed with a PMOS device formed using a replacement metal gate and a raised source drain. The raised source drain may be formed of epitaxially deposited silicon germanium material that is doped p-type. The replacement metal gate process results in a metal gate electrode and may involve the-removal of a nitride etch stop layer.
    Type: Application
    Filed: June 21, 2005
    Publication date: December 21, 2006
    Inventors: Jack Kavalieros, Annalisa Cappellani, Justin Brask, Mark Doczy, Matthew Metz, Suman Datta, Chris Barns, Robert Chau
  • Metal gate device with reduced oxidation of a high-k gate dielectric
    Publication number: 20060284271
    Abstract: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer and reduced oxidation of a substrate beneath the high-k gate dielectric layer. An oxygen barrier, or capping, layer on the high-k gate dielectric layer and metal gate may prevent such oxidation during processes such as spacer formation and annealing of ion implanted regions.
    Type: Application
    Filed: June 21, 2005
    Publication date: December 21, 2006
    Inventors: Brian Doyle, Jack Kavalieros, Justin Brask, Matthew Mertz, Mark Doczy, Suman Datta, Robert Chau
  • Method for fabricating transistor with thinned channel
    Publication number: 20060286755
    Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
    Type: Application
    Filed: June 15, 2005
    Publication date: December 21, 2006
    Inventors: Justin Brask, Robert Chau, Suman Datta, Mark Doczy, Brian Doyle, Jack Kavalieros, Amlan Majumdar, Matthew Metz, Marko Radosavljevic
  • Semiconductor device with a high-k gate dielectric and a metal gate electrode
    Publication number: 20060278941
    Abstract: A semiconductor device is described. That semiconductor device comprises a high-k gate dielectric layer that is formed on a substrate that applies strain to the high-k gate dielectric layer, and a metal gate electrode that is formed on the high-k gate dielectric layer.
    Type: Application
    Filed: June 13, 2005
    Publication date: December 14, 2006
    Inventors: Matthew Metz, Suman Datta, Mark Doczy, Justin Brask, Jack Kavalieros, Robert Chau
  • Polysilicon opening polish
    Patent number: 7144816
    Abstract: Fabricating a semiconductor structure includes providing a semiconductor substrate, forming a silicide layer over the substrate, and removing a portion of the silicide layer by chemical mechanical polishing. The fabrication of the structure can also include forming a dielectric layer after forming the silicide layer, and removing a portion of the dielectric layer by chemical mechanical polishing before removing the portion of the silicide layer.
    Type: Grant
    Filed: March 12, 2004
    Date of Patent: December 5, 2006
    Assignee: Intel Corporation
    Inventors: Chris E. Barns, Mark Doczy
  • Compensating for induced strain in the channels of metal gate transistors
    Publication number: 20060237801
    Abstract: Strained channel field effect transistors may have a threshold voltage shift. This threshold voltage shift may be compensated for by adjusting channel doping. But this also adversely affects mobility. The threshold voltage shift may be compensated, without adversely affecting mobility, by tailoring the workfunction of a metal gate electrode used in the transistor to adequately compensate for that threshold voltage shift. For example, in some embodiments, an appropriate metal may be selected with a slightly higher workfunction or, in other cases, the workfunction of a selected metal may be adjusted by, for example, doping the metal gate electrode with a material which increases the workfunction of the gate electrode.
    Type: Application
    Filed: April 20, 2005
    Publication date: October 26, 2006
    Inventors: Jack Kavalieros, Justin Brask, Mark Doczy, Matthew Metz, Suman Datta, Brian Doyle, Robert Chau
  • Methods of forming a multilayer stack alloy for work function engineering
    Patent number: 7122870
    Abstract: A method of forming a gate electrode is described, comprising forming a dielectric layer on a substrate, forming a first metal layer having a first work function on the dielectric layer, forming a second metal layer having a second work function on the first metal layer, such that a gate electrode is formed on the dielectric layer which has a work function that is determined from the work function of the alloy of the two types of metal. The work function of a microelectronic transistor can be varied or “tuned” depending on the precise definition and control of the metal types, layer sequence, individual layer thickness and total number of layers.
    Type: Grant
    Filed: August 9, 2004
    Date of Patent: October 17, 2006
    Assignee: Intel Corporation
    Inventors: John Barnak, Collin Borla, Mark Doczy, Markus Kuhn, Jacob M. Jensen
  • Semiconductor device with a high-k gate dielectric and a metal gate electrode
    Publication number: 20060220090
    Abstract: A semiconductor device is described. That semiconductor device comprises a high-k gate dielectric layer that is formed over a channel that is positioned within a substrate, and a metal gate electrode that is formed on the high-k gate dielectric layer. The high-k gate dielectric layer has off-state leakage characteristics that are superior to those of a silicon dioxide based gate dielectric, and on-state mobility characteristics that are superior to those of a high-k gate dielectric that comprises an isotropic material.
    Type: Application
    Filed: March 23, 2005
    Publication date: October 5, 2006
    Inventors: Matthew Metz, Suman Datta, Mark Doczy, Jack Kavalieros, Justin Brask, Brian Doyle, Marko Radosavljevic, Robert Chau
  • Using different gate dielectrics with NMOS and PMOS transistors of a complementary metal oxide semiconductor integrated circuit
    Publication number: 20060214237
    Abstract: Complementary metal oxide semiconductor integrated circuits may be formed with NMOS and PMOS transistors having different gate dielectrics. The different gate dielectrics may be formed, for example, by a replacement process. The gate dielectrics may differ in material, thickness, or formation techniques, as a few examples.
    Type: Application
    Filed: May 5, 2006
    Publication date: September 28, 2006
    Inventors: Matthew Metz, Suman Datta, Jack Kavalieros, Mark Doczy, Justin Brask, Robert Chau
  • Field effect transistor with metal source/drain regions
    Publication number: 20060202266
    Abstract: A semiconductor device comprising a gate electrode formed on a gate dielectric layer formed on a semiconductor film. A pair of source/drain regions are formed adjacent the channel region on opposite sides of the gate electrode. The source and drain regions each comprise a semiconductor portion adjacent to and in contact with the semiconductor channel and a metal portion adjacent to and in contact with the semiconductor portion.
    Type: Application
    Filed: March 14, 2005
    Publication date: September 14, 2006
    Inventors: Marko Radosavljevic, Suman Datta, Brian Doyle, Jack Kavalieros, Justin Brask, Mark Doczy, Amian Majumdar, Robert Chau
  • Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress
    Publication number: 20060205167
    Abstract: A transistor may be formed of different layers of silicon germanium, a lowest layer having a graded germanium concentration and upper layers having constant germanium concentrations such that the lowest layer is of the form Si1-xGex. The highest layer may be of the form Si1-yGey on the PMOS side. A source and drain may be formed of epitaxial silicon germanium of the form Si1-zGez on the PMOS side. In some embodiments, x is greater than y and z is greater than x in the PMOS device. Thus, a PMOS device may be formed with both uniaxial compressive stress in the channel direction and in-plane biaxial compressive stress. This combination of stress may result in higher mobility and increased device performance in some cases.
    Type: Application
    Filed: March 11, 2005
    Publication date: September 14, 2006
    Inventors: Jack Kavalieros, Justin Brask, Mark Doczy, Matthew Metz, Suman Datta, Brian Doyle, Robert Chau, Everett Wang, Philippe Matagne, Lucian Shifren, Been Jin, Mark Stettler, Martin Giles
  • Method for making a semiconductor device having a high-k gate dielectric
    Publication number: 20060189156
    Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer that contacts a metal oxide layer. The metal oxide layer is generated by forming a metal layer, then oxidizing the metal layer.
    Type: Application
    Filed: February 23, 2005
    Publication date: August 24, 2006
    Inventors: Mark Doczy, Jack Kavalieros, Justin Brask, Matthew Metz, Suman Datta, Brian Doyle, Robert Chau
  • Field effect transistor with narrow bandgap source and drain regions and method of fabrication
    Publication number: 20060186484
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Application
    Filed: February 23, 2005
    Publication date: August 24, 2006
    Inventors: Robert Chau, Suman Datta, Jack Kavalieros, Justin Brask, Mark Doczy, Matthew Metz
  • Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
    Publication number: 20060180878
    Abstract: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, then forming a trench within the first dielectric layer. After forming a second dielectric layer on the substrate, a first metal layer is formed within the trench on a first part of the second dielectric layer. A second metal layer is then formed on the first metal layer and on a second part of the second dielectric layer.
    Type: Application
    Filed: March 29, 2006
    Publication date: August 17, 2006
    Inventors: Justin Brask, Jack Kavalieros, Mark Doczy, Uday Shah, Chris Barns, Matthew Metz, Suman Datta, Annalisa Cappellani, Robert Chau
  • Method for making a semiconductor device with a metal gate electrode that is formed on an annealed high-k gate dielectric layer
    Publication number: 20060183277
    Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, and forming a sacrificial layer on the high-k gate dielectric layer. After etching the sacrificial layer, first and second spacers are formed on opposite sides of the sacrificial layer. After removing the sacrificial layer to generate a trench that is positioned between the first and second spacers, a metal layer is formed on the high-k gate dielectric layer.
    Type: Application
    Filed: December 19, 2003
    Publication date: August 17, 2006
    Inventors: Justin Brask, Mark Doczy, Jack Kavalieros, Uday Shah, Matthew Metz, Chris Barns, Suman Datta, Christopher Thomas, Robert Chau
  • Method for making a semiconductor device having a high-k gate dielectric
    Publication number: 20060166447
    Abstract: A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.
    Type: Application
    Filed: March 27, 2006
    Publication date: July 27, 2006
    Inventors: Mark Doczy, Gilbert Dewey, Suman Datta, Sangwoo Pae, Justin Brask, Jack Kavalieros, Matthew Metz, Adrian Sherrill, Markus Kuhn, Robert Chau
  • Inhibiting growth under high dielectric constant films
    Publication number: 20060160371
    Abstract: Oxidation between a higher dielectric constant material such as a rare earth oxide and a substrate may be reduced by providing a seal layer over the gate dielectric. In some embodiments, the seal layer may be isolated from the gate dielectric by a buffer layer.
    Type: Application
    Filed: January 18, 2005
    Publication date: July 20, 2006
    Inventors: Matthew Metz, Suman Datta, Jack Kavalieros, Mark Doczy, Justin Brask, Robert Chau
  • Forming dual metal complementary metal oxide semiconductor integrated circuits
    Publication number: 20060160342
    Abstract: Complementary metal oxide semiconductor metal gate transistors may be formed by depositing a metal layer in trenches formerly inhabited by patterned gate structures. The patterned gate structures may have been formed of polysilicon in one embodiment. The trenches may be filled with metal by surface activating using a catalytic metal, followed by electroless deposition of a seed layer followed by superconformal filling bottom up.
    Type: Application
    Filed: January 18, 2005
    Publication date: July 20, 2006
    Inventors: Mark Doczy, Lawrence Wong, Valery Dubin, Justin Brask, Jack Kavalieros, Suman Datta, Matthew Metz, Robert Chau