Patents by Inventor Mark Doczy

Mark Doczy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • In-situ cleaning of light source collector optics
    Publication number: 20060000489
    Abstract: A method for cleaning optics in a chamber. The method can include introducing a first etchant into a chamber that encloses an optical component and a source of electromagnetic radiation that is suitable for lithography, ionizing the first etchant, and removing debris from a surface of the optical component.
    Type: Application
    Filed: August 30, 2005
    Publication date: January 5, 2006
    Inventors: Michael Chan, Robert Bristol, Mark Doczy
  • Forming high-k dielectric layers on smooth substrates
    Publication number: 20060001071
    Abstract: A buffer layer and a high-k metal oxide dielectric may be formed over a smooth silicon substrate. The substrate smoothness may reduce column growth of the high-k metal oxide gate dielectric. The surface of the substrate may be saturated with hydroxyl terminations prior to deposition.
    Type: Application
    Filed: June 30, 2004
    Publication date: January 5, 2006
    Inventors: Justin Brask, Jack Kavalieros, Mark Doczy, Matthew Metz, Suman Datta, Uday Shah, Gilbert Dewey, Robert Chau
  • Using different gate dielectrics with NMOS and PMOS transistors of a complementary metal oxide semiconductor integrated circuit
    Publication number: 20060001106
    Abstract: Complementary metal oxide semiconductor integrated circuits may be formed with NMOS and PMOS transistors having different gate dielectrics. The different gate dielectrics may be formed, for example, by a replacement process. The gate dielectrics may differ in material, thickness, or formation techniques, as a few examples.
    Type: Application
    Filed: June 30, 2004
    Publication date: January 5, 2006
    Inventors: Matthew Metz, Suman Datta, Jack Kavalieros, Mark Doczy, Justin Brask, Robert Chau
  • Reducing the dielectric constant of a portion of a gate dielectric
    Publication number: 20050285213
    Abstract: In a metal gate replacement process, a cup-shaped gate metal oxide dielectric may have a vertical portion that may be exposed to a silicon ion implantation. As a result of the implantation, the dielectric constant of a vertical portion may be reduced, reducing fringe capacitance.
    Type: Application
    Filed: June 24, 2004
    Publication date: December 29, 2005
    Inventors: Suman Datta, Jack Kavalieros, Mark Doczy, Matthew Metz, Justin Brask, Robert Chau
  • Reducing reactions between polysilicon gate electrodes and high dielectric constant gate dielectrics
    Publication number: 20050287748
    Abstract: In a metal gate replacement process, a gate electrode stack may be formed of a dielectric covered by a sacrificial metal layer covered by a polysilicon gate electrode. In subsequent processing of the source/drains, high temperature steps may be utilized. The sacrificial metal layer prevents reactions between the polysilicon gate electrode and the underlying high dielectric constant dielectric. As a result, adverse consequences of the reaction between the polysilicon and the high dielectric constant dielectric material can be reduced.
    Type: Application
    Filed: June 24, 2004
    Publication date: December 29, 2005
    Inventors: Jack Kavalieros, Justin Brask, Mark Doczy, Uday Shah, Matthew Metz, Suman Datta, Robert Chau
  • Facilitating removal of sacrificial layers to form replacement metal gates
    Publication number: 20050287746
    Abstract: In a metal gate replacement process, a gate electrode stack may be formed of a germanium containing layer. In subsequent processing of the source/drains, high temperature steps may be utilized, forming a germinide on said stacks. That germinide may be removed, prior to removing the rest of the stack, using H2O2.
    Type: Application
    Filed: June 24, 2004
    Publication date: December 29, 2005
    Inventors: Matthew Metz, Suman Datta, Jack Kavalieros, Mark Doczy, Justin Brask, Robert Chau
  • Transition metal alloys for use as a gate electrode and devices incorporating these alloys
    Publication number: 20050280050
    Abstract: Embodiments of a transition metal alloy having an n-type or p-type work function that does not significantly shift at elevated temperature. The disclosed transition metal alloys may be used as, or form a part of, the gate electrode in a transistor. Methods of forming a gate electrode using these transition metal alloys are also disclosed.
    Type: Application
    Filed: August 11, 2005
    Publication date: December 22, 2005
    Inventors: Mark Doczy, Nathan Baxter, Robert Chau, Kari Harkonen, Teemu Lang
  • Replacement gate process for making a semiconductor device that includes a metal gate electrode
    Publication number: 20050272191
    Abstract: A method for making a semiconductor device is described. That method comprises forming a sacrificial layer on a substrate, and forming a trench within the sacrificial layer. After forming a dummy gate electrode within the trench, a hard mask is formed on the dummy gate electrode and within the trench.
    Type: Application
    Filed: June 3, 2004
    Publication date: December 8, 2005
    Inventors: Uday Shah, Mark Doczy, Justin Brask, Jack Kavalieros, Matthew Metz, Robert Chau, Chris Barns
  • Forming integrated circuits with replacement metal gate electrodes
    Publication number: 20050269644
    Abstract: In a metal gate replacement process, a stack of at least two polysilicon layers or other materials may be formed. Sidewall spacers may be formed on the stack. The stack may then be planarized. Next, the upper layer of the stack may be selectively removed. Then, the exposed portions of the sidewall spacers may be selectively removed. Finally, the lower portion of the stack may be removed to form a T-shaped trench which may be filled with the metal replacement.
    Type: Application
    Filed: June 8, 2004
    Publication date: December 8, 2005
    Inventors: Justin Brask, Jack Kavalieros, Mark Doczy, Matthew Metz, Suman Datta, Uday Shah, Brian Doyle, Robert Chau
  • Method for making a semiconductor device with a high-k gate dielectric and metal layers that meet at a P/N junction
    Publication number: 20050272270
    Abstract: A method for making a semiconductor device is described. That method comprises modifying a first surface, and forming a high-k gate dielectric layer on an unmodified second surface.
    Type: Application
    Filed: April 18, 2005
    Publication date: December 8, 2005
    Inventors: Matthew Metz, Suman Datta, Jack Kavalieros, Mark Doczy, Justin Brask, Uday Shah, Robert Chau
  • integrating n-type and P-type metal gate transistors
    Patent number: 6972225
    Abstract: At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.
    Type: Grant
    Filed: September 20, 2004
    Date of Patent: December 6, 2005
    Assignee: Intel Corporation
    Inventors: Mark Doczy, Justin K. Brask, Steven J. Keating, Chris E. Barns, Brian S. Doyle, Michael L. McSwiney, Jack T. Kavalieros, John P. Barnak
  • Method for making a semiconductor device with a high-k gate dielectric and a conductor that facilitates current flow across a P/N junction
    Publication number: 20050266619
    Abstract: A method for making a semiconductor device is described. That method comprises forming on a substrate a first gate dielectric layer that has a first substantially vertical component, then forming a first metal layer on the first gate dielectric layer. After forming on the substrate a second gate dielectric layer that has a second substantially vertical component, a second metal layer is formed on the second gate dielectric layer. In this method, a conductor is formed that contacts both the first metal layer and the second metal layer.
    Type: Application
    Filed: May 26, 2004
    Publication date: December 1, 2005
    Inventors: Justin Brask, Jack Kavalieros, Mark Doczy, Matthew Metz, Uday Shah, Chris Barns, Suman Datta, Robert Turkot, Robert Chau
  • Modifying the viscosity of etchants
    Publication number: 20050263483
    Abstract: Semiconductor integrated circuit structures, such as stacks containing metal layers, may be etched with a modified viscosity etchant. An increased viscosity etchant, for example, may reduce undercutting when a metal film is being etched.
    Type: Application
    Filed: August 3, 2005
    Publication date: December 1, 2005
    Inventors: Justin Brask, Jack Kavalieros, Mark Doczy, Matthew Metz, Suman Datta, Uday Shah, Robert Chau
  • Controlling bubble formation during etching
    Publication number: 20050266694
    Abstract: A wafer may be rotated while etching to displace bubbles that may form, for example, from a reaction between silicon and water. As a result, a hydrophobic layer, which would otherwise be created by the bubbles, cannot form, resulting in a more uniform etch rate in some embodiments.
    Type: Application
    Filed: May 27, 2004
    Publication date: December 1, 2005
    Inventors: Justin Brask, Paul Sears, Jack Kavalieros, Mark Doczy, Matthew Metz, Suman Datta, Uday Shah, Robert Chau
  • In-situ cleaning of light source collector optics
    Patent number: 6968850
    Abstract: A method and system for cleaning collector optics in a light source chamber. In producing, for example, extreme ultraviolet light for lithography, debris such as tungsten can accumulate on optical components near a light source in the light source chamber. An etchant, such as a fluorine-containing gas, can be introduced into the light source chamber. The etchant is ionized via electrodes to generate free fluorine. The electrodes can be, for example, existing light source chamber components including the optical components. The fluorine can then react with the debris, forming gaseous compounds, which are pumped out of the light source chamber.
    Type: Grant
    Filed: July 15, 2002
    Date of Patent: November 29, 2005
    Assignee: Intel Corporation
    Inventors: Michael Chan, Robert Bristol, Mark Doczy
  • Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
    Publication number: 20050250258
    Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, and forming a masking layer on a first part of the high-k gate dielectric layer. After forming a first metal layer on the masking layer and on an exposed second part of the high-k gate dielectric layer, the masking layer is removed. A second metal layer is then formed on the first metal layer and on the first part of the high-k gate dielectric layer.
    Type: Application
    Filed: May 4, 2004
    Publication date: November 10, 2005
    Inventors: Matthew Metz, Suman Datta, Jack Kavalieros, Mark Doczy, Justin Brask, Robert Chau
  • Reducing gate dielectric material to form a metal gate electrode extension
    Publication number: 20050245036
    Abstract: In a metal gate replacement process, a cup-shaped gate metal oxide dielectric may have vertical portions that may be exposed to a reduction reaction. As a result of the reduction reaction, the vertical portions may be converted to metal, which adds to the existing gate electrode. In some cases, removing the vertical dielectric portions reduces fringe capacitance and may also advantageously slightly increased underdiffusion without adding heat, in some embodiments.
    Type: Application
    Filed: April 30, 2004
    Publication date: November 3, 2005
    Inventors: Suman Datta, Justin Brask, Jack Kavalieros, Mark Doczy, Matthew Metz, Robert Chau
  • Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
    Publication number: 20050233527
    Abstract: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, then forming a trench within the first dielectric layer. After forming a second dielectric layer on the substrate, a first metal layer is formed within the trench on a first part of the second dielectric layer. A second metal layer is then formed on the first metal layer and on a second part of the second dielectric layer.
    Type: Application
    Filed: April 20, 2004
    Publication date: October 20, 2005
    Inventors: Justin Brask, Jack Kavalieros, Mark Doczy, Uday Shah, Chris Barns, Matthew Metz, Suman Datta, Annalisa Cappellani, Robert Chau
  • Enhanced gate structure
    Publication number: 20050233530
    Abstract: A technique for producing an enhanced gate structure having a silicon-nitride buffer. Embodiments relate to the structure and development of a gate structure having a silicon-nitride buffer layer deposited upon a dielectric layer, upon which a gate material, such as polysilicon, is deposited.
    Type: Application
    Filed: June 15, 2005
    Publication date: October 20, 2005
    Inventors: John Barnak, Mark Doczy, Robert Chau, Collin Borla
  • Semiconductor device having a laterally modulated gate workfunction and method of fabrication
    Publication number: 20050224886
    Abstract: A transistor comprising a gate electrode formed on a gate dielectric layer formed on a substrate. A pair of source/drain regions are formed in the substrate on opposite sides of the laterally opposite sidewalls of the gate electrode. The gate electrode has a central portion formed on the gate dielectric layer and over the substrate region between the source and drain regions and a pair sidewall portions which overlap a portion of the source/drain regions wherein the central portion has a first work function and said pair of sidewall portions has a second work function, wherein the second work function is different than the first work function.
    Type: Application
    Filed: March 31, 2004
    Publication date: October 13, 2005
    Inventors: Brian Doyle, Scott Hareland, Mark Doczy, Robert Chau