Patents by Inventor Mark Doczy

Mark Doczy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for making a semiconductor device that includes a metal gate electrode
    Publication number: 20060051957
    Abstract: A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer and a sacrificial structure that comprises a first layer and a second layer, such that the second layer is formed on the first layer and is wider than the first layer. After the sacrificial structure is removed to generate a trench, a metal gate electrode is formed within the trench.
    Type: Application
    Filed: September 7, 2004
    Publication date: March 9, 2006
    Inventors: Justin Brask, Jack Kavalieros, Mark Doczy, Matthew Metz, Suman Datta, Uday Shah, Brian Doyle, Robert Chau
  • Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
    Publication number: 20060051924
    Abstract: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, a trench within the first dielectric layer, and a second dielectric layer on the substrate. The second dielectric layer has a first part that is formed in the trench and a second part. After a first metal layer with a first workfunction is formed on the first and second parts of the second dielectric layer, part of the first metal layer is converted into a second metal layer with a second workfunction.
    Type: Application
    Filed: September 8, 2004
    Publication date: March 9, 2006
    Inventors: Mark Doczy, Justin Brask, Jack Kavalieros, Uday Shah, Matthew Metz, Suman Datta, Ramune Nagisetty, Robert Chau
  • Method for making a semiconductor device having a high-k gate dielectric
    Publication number: 20060051882
    Abstract: A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.
    Type: Application
    Filed: August 22, 2005
    Publication date: March 9, 2006
    Inventors: Mark Doczy, Gilbert Dewey, Suman Datta, Sangwoo Pae, Justin Brask, Jack Kavalieros, Matthew Metz, Adrian Sherrill, Markus Kuhn, Robert Chau
  • Method for making a semiconductor device having a high-k gate dielectric
    Publication number: 20060051880
    Abstract: A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.
    Type: Application
    Filed: September 7, 2004
    Publication date: March 9, 2006
    Inventors: Mark Doczy, Gilbert Dewey, Suman Datta, Sangwoo Pae, Justin Brask, Jack Kavalieros, Matthew Metz, Adrian Sherrill, Markus Kuhn, Robert Chau
  • Facilitating removal of sacrificial layers to form replacement metal gates
    Publication number: 20060046523
    Abstract: Replacement metal gates may be formed by removing a polysilicon layer from a gate structure. The gate structure may be formed by patterning the polysilicon layer and depositing a spacer layer over the gate structure such that the spacer layer has a first polish rate. The spacer layer is then etched to form a sidewall spacer. An interlayer dielectric is applied over the gate structure with the sidewall spacer. The interlayer dielectric has a second polish rate higher than the first polish rate. In one embodiment, the interlayer dielectric has a lower polish rate than that of oxide.
    Type: Application
    Filed: August 25, 2004
    Publication date: March 2, 2006
    Inventors: Jack Kavalieros, Justin Brask, Mark Doczy, Chris Barns, Matthew Metz, Suman Datta, Robert Chau, Matt Prince, Anne Miller, Mark Buehler
  • Forming integrated circuits with replacement metal gate electrodes
    Publication number: 20060046401
    Abstract: In a metal gate replacement process, a stack of at least two polysilicon layers or other materials may be formed. Sidewall spacers may be formed on the stack. The stack may then be planarized. Next, the upper layer of the stack may be selectively removed. Then, the exposed portions of the sidewall spacers may be selectively removed. Finally, the lower portion of the stack may be removed to form a T-shaped trench which may be filled with the metal replacement.
    Type: Application
    Filed: August 25, 2004
    Publication date: March 2, 2006
    Inventors: Jack Kavalieros, Justin Brask, Mark Doczy, Matthew Metz, Suman Datta, Uday Shah, Robert Chau
  • Atomic layer deposition of high quality high-k transition metal and rare earth oxides
    Publication number: 20060045968
    Abstract: Increasing the number of successive pulses of oxidant before applying pulses of metal precursor may improve the quality of the resulting metal or rare earth oxide films. These metal or rare earth oxide films may be utilized for high dielectric constant gate dielectrics. In addition, pulsing the oxidant during the pre-stabilization period may be advantageous. Also, using more pulses of oxidant than the pulses of precursor may reduce chlorine concentration in the resulting films.
    Type: Application
    Filed: August 25, 2004
    Publication date: March 2, 2006
    Inventors: Matthew Metz, Mark Brazier, Timothy Glassman, Christopher Thomas, Lawrence Foley, Christopher Parker, Ying Zhou, Markus Kuhn, Suman Datta, Jack Kavalieros, Mark Doczy, Justin Brask, Robert Chau
  • Forming abrupt source drain metal gate transistors
    Publication number: 20060046399
    Abstract: A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved.
    Type: Application
    Filed: August 25, 2004
    Publication date: March 2, 2006
    Inventors: Nick Lindert, Suman Datta, Jack Kavalieros, Mark Doczy, Matthew Metz, Justin Brask, Robert Chau, Mark Bohr, Anand Murthy
  • Facilitating removal of sacrificial layers via implantation to form replacement metal gates
    Publication number: 20060046448
    Abstract: Replacement metal gates may be formed by removing a polysilicon layer from a gate structure. The gate structure may be formed by patterning the polysilicon layer and depositing a spacer layer over the gate structure such that the spacer layer has a first polish rate. The spacer layer is then etched to form a sidewall spacer. An interlayer dielectric is applied over the gate structure with the sidewall spacer. The interlayer dielectric has a second polish rate higher than the first polish rate. A hard mask may also be applied over the gate structure and implanted so that the hard mask may be more readily removed.
    Type: Application
    Filed: August 25, 2004
    Publication date: March 2, 2006
    Inventors: Chris Barns, Matt Prince, Mark Doczy, Justin Brask, Jack Kavalieros
  • Metal-gate electrode for CMOS transistor applications
    Patent number: 6998686
    Abstract: Described is a CMOS transistor structure with a multi-layered gate electrode structure and a method of fabrication. The gate electrode structure has a three-layered metallic gate electrode and a polysilicon layer. The first metallic layer acts as a barrier to prevent the second metallic layer from reacting with an underlying dielectric. The second metallic layer acts to set the work function of the gate electrode structure. The third metallic layer acts as a barrier to prevent the second metallic layer from reacting with the polysilicon layer. The method of fabricating the gate electrode structure includes forming the three metallic layers thick enough that each layer provides the barrier and work-function setting functions mentioned above, but also thin enough that a subsequent wet-etch can be performed without excessive undercutting of the metallic layers.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: February 14, 2006
    Assignee: Intel Corporation
    Inventors: Robert Chau, Mark Doczy, Brian Doyle, Jack Kavalieros
  • Integrating n-type and p-type metal gate transistors
    Publication number: 20060030104
    Abstract: At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.
    Type: Application
    Filed: October 11, 2005
    Publication date: February 9, 2006
    Inventors: Mark Doczy, Justin Brask, Steven Keating, Chris Barns, Brian Doyle, Michael McSwiney, Jack Kavalieros, John Barnak
  • Compensating the workfunction of a metal gate transistor for abstraction by the gate dielectric layer
    Publication number: 20060024892
    Abstract: A metal gate transistor may include a metal layer over a high dielectric constant dielectric layer. The dielectric layer abstracts electronegativity from said metal layer, altering its workfunction. The workfunction of the metal layer may be set to compensate for the dielectric layer abstraction.
    Type: Application
    Filed: July 28, 2004
    Publication date: February 2, 2006
    Inventors: Justin Brask, Jack Kavalieros, Mark Doczy, Matthew Metz, Suman Datta, Uday Shah, Robert Chau
  • Planarizing a semiconductor structure to form replacement metal gates
    Publication number: 20060022277
    Abstract: A sacrificial gate structure, including nitride and fill layers, may be replaced with a metal gate electrode. The metal gate electrode may again be covered with a nitride layer covered by a fill layer. The replacement of the nitride and fill layers may reintroduce strain and provide an etch stop.
    Type: Application
    Filed: July 28, 2004
    Publication date: February 2, 2006
    Inventors: Jack Kavalieros, Justin Brask, Mark Doczy, Uday Shah, Chris Barns, Matthew Metz, Suman Datta, Robert Chau
  • Using different gate dielectrics with NMOS and PMOS transistors of a complementary metal oxide semiconductor integrated circuit
    Publication number: 20060022271
    Abstract: Complementary metal oxide semiconductor integrated circuits may be formed with NMOS and PMOS transistors having different gate dielectrics. The different gate dielectrics may be formed, for example, by a subtractive process. The gate dielectrics may differ in material, thickness, or formation techniques, as a few examples.
    Type: Application
    Filed: July 28, 2004
    Publication date: February 2, 2006
    Inventors: Matthew Metz, Suman Datta, Jack Kavalieros, Mark Doczy, Justin Brask, Robert Chau
  • Semiconductor device with a high-k gate dielectric and a metal gate electrode
    Publication number: 20060017098
    Abstract: A semiconductor device is described that comprises a gate dielectric and a metal gate electrode that comprises an aluminide.
    Type: Application
    Filed: July 20, 2004
    Publication date: January 26, 2006
    Inventors: Mark Doczy, Jack Kavalieros, Matthew Metz, Justin Brask, Suman Datta, Robert Chau
  • Novel metal-gate electrode for CMOS transistor applications
    Publication number: 20060017122
    Abstract: Described is a CMOS transistor structure with a multi-layered gate electrode structure and a method of fabrication. The gate electrode structure has a three-layered metallic gate electrode and a polysilicon layer. The first metallic layer acts as a barrier to prevent the second metallic layer from reacting with an underlying dielectric. The second metallic layer acts to set the work function of the gate electrode structure. The third metallic layer acts as a barrier to prevent the second metallic layer from reacting with the polysilicon layer. The method of fabricating the gate electrode structure includes forming the three metallic layers thick enough that each layer provides the barrier and work-function setting functions mentioned above, but also thin enough that a subsequent wet-etch can be performed without excessive undercutting of the metallic layers.
    Type: Application
    Filed: September 20, 2005
    Publication date: January 26, 2006
    Inventors: Robert Chau, Mark Doczy, Brian Doyle, Jack Kavalieros
  • Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
    Publication number: 20060008968
    Abstract: A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, forming a trench within the dielectric layer, and forming a high-k gate dielectric layer within the trench. After forming a first metal layer on the high-k gate dielectric layer, a second metal layer is formed on the first metal layer. At least part of the second metal layer is removed from above the dielectric layer using a polishing step, and additional material is removed from above the dielectric layer using an etch step.
    Type: Application
    Filed: July 6, 2004
    Publication date: January 12, 2006
    Inventors: Justin Brask, Chris Barns, Mark Doczy, Uday Shah, Jack Kavalieros, Matthew Metz, Suman Datta, Anne Miller, Robert Chau
  • Methods for integrating replacement metal gate structures
    Publication number: 20060008954
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods comprise providing a substrate comprising a first transistor structure comprising an n-type gate material and second transistor structure comprising a p-type gate material, selectively removing the n-type gate material to form a recess in the first gate structure, and then filling the recess with an n-type metal gate material.
    Type: Application
    Filed: September 2, 2005
    Publication date: January 12, 2006
    Inventors: Jack Kavalieros, Justin Brask, Mark Doczy, Scott Hareland, Matthew Metz, Chris Barns, Robert Chau
  • Forming dual metal complementary metal oxide semiconductor integrated circuits
    Publication number: 20060006522
    Abstract: Complementary metal oxide semiconductor metal gate transistors may be formed by depositing a metal layer in trenches formerly inhabited by patterned gate structures. The patterned gate structures may have been formed of polysilicon in one embodiment. The metal layer may have a workfunction most suitable for forming one type of transistor, but is used to form both the n and p-type transistors. The workfunction of the metal layer may be converted, for example, by ion implantation to make it more suitable for use in forming transistors of the opposite type.
    Type: Application
    Filed: July 12, 2004
    Publication date: January 12, 2006
    Inventors: Mark Doczy, Mitchell Taylor, Justin Brask, Jack Kavalieros, Suman Datta, Matthew Metz, Robert Chau, Jack Hwang
  • Removing a high-k gate dielectric
    Publication number: 20060003499
    Abstract: A metal oxide layer on a substrate is converted at least partly to a metal layer. At least part of the metal layer is covered by an oxidation resistant cover. The covered layer and underlying metal may be removed, for example, using acid.
    Type: Application
    Filed: June 30, 2004
    Publication date: January 5, 2006
    Inventors: Mark Doczy, Robert Norman, Justin Brask, Jack Kavalieros, Matthew Metz, Suman Datta, Robert Chau