Patents by Inventor Mark L. Doczy

Mark L. Doczy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DIELECTRIC INTERFACE FOR GROUP III-V SEMICONDUCTOR DEVICE
    Publication number: 20090095984
    Abstract: A Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region.
    Type: Application
    Filed: December 18, 2008
    Publication date: April 16, 2009
    Inventors: Justin K. Brask, Suman Datta, Mark L. Doczy, James M. Blackwell, Matthew V. Metz, Jack T. Kavalieros, Robert S. Chau
  • Field effect transistor with narrow bandgap source and drain regions and method of fabrication
    Patent number: 7518196
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: April 14, 2009
    Assignee: Intel Corporation
    Inventors: Robert S. Chau, Suman Datta, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz
  • PROCESS FOR INTEGRATING PLANAR AND NON-PLANAR CMOS TRANSISTORS ON A BULK SUBSTRATE AND ARTICLE MADE THEREBY
    Publication number: 20090090976
    Abstract: A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.
    Type: Application
    Filed: December 11, 2008
    Publication date: April 9, 2009
    Applicant: Intel Corporation
    Inventors: Jack T. Kavalieros, Justin K. Brask, Brian S. Doyle, Uday Shah, Suman Datta, Mark L. Doczy, Matthew V. Metz, Robert S. Chau
  • Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress
    Publication number: 20090075445
    Abstract: A transistor may be formed of different layers of silicon germanium, a lowest layer having a graded germanium concentration and upper layers having constant germanium concentrations such that the lowest layer is of the form Si1-xGex. The highest layer may be of the form Si1-yGey on the PMOS side. A source and drain may be formed of epitaxial silicon germanium of the form Si1-zGez on the PMOS side. In some embodiments, x is greater than y and z is greater than x in the PMOS device. Thus, a PMOS device may be formed with both uniaxial compressive stress in the channel direction and in-plane biaxial compressive stress. This combination of stress may result in higher mobility and increased device performance in some cases.
    Type: Application
    Filed: November 19, 2008
    Publication date: March 19, 2009
    Inventors: Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew V. Metz, Suman Datta, Brian S. Doyle, Robert S. Chau, Everett X. Wang, Philippe Matagne, Lucian Shifren, Been Y. Jin, Mark Stettler, Martin D. Giles
  • Metal gate device with reduced oxidation of a high-k gate dielectric
    Patent number: 7501336
    Abstract: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer and reduced oxidation of a substrate beneath the high-k gate dielectric layer. An oxygen barrier, or capping, layer on the high-k gate dielectric layer and metal gate may prevent such oxidation during processes such as spacer formation and annealing of ion implanted regions.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: March 10, 2009
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, Jack Kavalieros, Justin K. Brask, Matthew V. Mertz, Mark L. Doczy, Suman Datta, Robert S. Chau
  • Semiconductor device with a high-k gate dielectric and a metal gate electrode
    Publication number: 20090039446
    Abstract: A semiconductor device is described. That semiconductor device comprises a high-k gate dielectric layer that is formed on a substrate that applies strain to the high-k gate dielectric layer, and a metal gate electrode that is formed on the high-k gate dielectric layer.
    Type: Application
    Filed: October 7, 2008
    Publication date: February 12, 2009
    Inventors: Matthew V. Metz, Suman Datta, Mark L. Doczy, Justin K. Brask, Jack Kavalieros, Robert S. Chau
  • Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
    Publication number: 20090042405
    Abstract: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, a trench within the first dielectric layer, and a second dielectric layer on the substrate. The second dielectric layer has a first part that is formed in the trench and a second part. After a first metal layer with a first workfunction is formed on the first and second parts of the second dielectric layer, part of the first metal layer is converted into a second metal layer with a second workfunction.
    Type: Application
    Filed: June 12, 2008
    Publication date: February 12, 2009
    Inventors: Mark L. Doczy, Justin K. Brask, Jack Kavalieros, Uday Shah, Matthew V. Metz, Suman Datta, Ramune Nagisetty, Robert S. Chau
  • Dielectric interface for group III-V semiconductor device
    Patent number: 7485503
    Abstract: A Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: February 3, 2009
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Suman Datta, Mark L. Doczy, James M. Blackwell, Matthew V. Metz, Jack T. Kavalieros, Robert S. Chau
  • METHOD FOR MAKING A SEMICONDUCTOR DEVICE HAVING A HIGH-K GATE DIELECTRIC
    Publication number: 20090020836
    Abstract: A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.
    Type: Application
    Filed: February 29, 2008
    Publication date: January 22, 2009
    Inventors: Mark L. Doczy, Gilbert Dewey, Suman Datta, Sangwoo Pae, Justin K. Brask, Jack Kavalieros, Matthew V. Metz, Adrian B. Sherrill, Markus Kuhn, Robert S. Chau
  • Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
    Patent number: 7479421
    Abstract: A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: January 20, 2009
    Assignee: Intel Corporation
    Inventors: Jack T. Kavalieros, Justin K. Brask, Brian S. Doyle, Uday Shah, Suman Datta, Mark L. Doczy, Matthew V. Metz, Robert S. Chau
  • Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress
    Patent number: 7470972
    Abstract: A transistor may be formed of different layers of silicon germanium, a lowest layer having a graded germanium concentration and upper layers having constant germanium concentrations such that the lowest layer is of the form Si1-xGex. The highest layer may be of the form Si1-yGey on the PMOS side. A source and drain may be formed of epitaxial silicon germanium of the form Si1-zGez on the PMOS side. In some embodiments, x is greater than y and z is greater than x in the PMOS device. Thus, a PMOS device may be formed with both uniaxial compressive stress in the channel direction and in-plane biaxial compressive stress. This combination of stress may result in higher mobility and increased device performance in some cases.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: December 30, 2008
    Assignee: Intel Corporation
    Inventors: Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew V. Metz, Suman Datta, Brian S. Doyle, Robert S. Chau, Everett X. Wang, Philippe Matagne, Lucian Shifren, Been Y. Jin, Mark Stettler, Martin D. Giles
  • Semiconductor device with a high-k gate dielectric and a metal gate electrode
    Patent number: 7449756
    Abstract: A semiconductor device is described. That semiconductor device comprises a high-k gate dielectric layer that is formed on a substrate that applies strain to the high-k gate dielectric layer, and a metal gate electrode that is formed on the high-k gate dielectric layer.
    Type: Grant
    Filed: June 13, 2005
    Date of Patent: November 11, 2008
    Assignee: Intel Corporation
    Inventors: Matthew V. Metz, Suman Datta, Mark L. Doczy, Justin K. Brask, Jack Kavalieros, Robert S. Chau
  • Method for making a semiconductor device having a high-k gate dielectric
    Patent number: 7442983
    Abstract: A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.
    Type: Grant
    Filed: March 27, 2006
    Date of Patent: October 28, 2008
    Assignee: Intel Corporation
    Inventors: Mark L. Doczy, Gilbert Dewey, Suman Datta, Sangwoo Pae, Justin K. Brask, Jack Kavalieros, Matthew V. Metz, Adrian B. Sherrill, Markus Kuhn, Robert S. Chau
  • Block Contact Architectures for Nanoscale Channel Transistors
    Publication number: 20080258207
    Abstract: A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.
    Type: Application
    Filed: September 14, 2007
    Publication date: October 23, 2008
    Inventors: Marko Radosavljevic, Amlan Majumdar, Brian S. Doyle, Jack Kavalieros, Mark L. Doczy, Justin K. Brask, Uday Shah, Suman Datta, Robert S. Chau
  • Method for fabricating metal gate structures
    Patent number: 7439571
    Abstract: Methods of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising source/drain and gate regions, wherein the gate region comprises a metal layer disposed on a gate dielectric layer, and then laser annealing the substrate.
    Type: Grant
    Filed: May 2, 2005
    Date of Patent: October 21, 2008
    Assignee: Intel Corporation
    Inventors: Mark L. Doczy, Mark Y. Liu, Jack Kavalieros, Justin K. Brask, Matthew V. Metz, Robert S. Chau
  • Sb-based CMOS devices
    Patent number: 7429747
    Abstract: A group III-V material CMOS device may have NMOS and PMOS portions that are substantially the same through several of their layers. This may make the CMOS device easy to make and prevent coefficient of thermal expansion mismatches between the NMOS and PMOS portions.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: September 30, 2008
    Assignee: Intel Corporation
    Inventors: Mantu K. Hudait, Suman Datta, Jack T. Kavalieros, Mark L. Doczy, Robert S. Chau
  • Uniform silicide metal on epitaxially grown source and drain regions of three-dimensional transistors
    Patent number: 7425500
    Abstract: A method for fabricating a three-dimensional transistor is described. Atomic Layer Deposition of nickel, in one embodiment, is used to form a uniform silicide on all epitaxially grown source and drain regions, including those facing downwardly.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: September 16, 2008
    Assignee: Intel Corporation
    Inventors: Matthew V. Metz, Suman Datta, Mark L. Doczy, Jack T. Kavalieros, Justin K. Brask, Robert S. Chau
  • Reducing reactions between polysilicon gate electrodes and high dielectric constant gate dielectrics
    Patent number: 7425490
    Abstract: In a metal gate replacement process, a gate electrode stack may be formed of a dielectric covered by a sacrificial metal layer covered by a polysilicon gate electrode. In subsequent processing of the source/drains, high temperature steps may be utilized. The sacrificial metal layer prevents reactions between the polysilicon gate electrode and the underlying high dielectric constant dielectric. As a result, adverse consequences of the reaction between the polysilicon and the high dielectric constant dielectric material can be reduced.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: September 16, 2008
    Assignee: Intel Corporation
    Inventors: Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Uday Shah, Matthew Metz, Suman Datta, Robert S. Chau
  • Facilitating removal of sacrificial layers via implantation to form replacement metal gates
    Patent number: 7422936
    Abstract: Replacement metal gates may be formed by removing a polysilicon layer from a gate structure. The gate structure may be formed by patterning the polysilicon layer and depositing a spacer layer over the gate structure such that the spacer layer has a first polish rate. The spacer layer is then etched to form a sidewall spacer. An interlayer dielectric is applied over the gate structure with the sidewall spacer. The interlayer dielectric has a second polish rate higher than the first polish rate. A hard mask may also be applied over the gate structure and implanted so that the hard mask may be more readily removed.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: September 9, 2008
    Assignee: Intel Corporation
    Inventors: Chris E. Barns, Matt Prince, Mark L. Doczy, Justin K. Brask, Jack Kavalieros
  • Reducing oxidation under a high K gate dielectric
    Publication number: 20080211033
    Abstract: A metal layer is formed on a dielectric layer, which is formed on a substrate. After forming a masking layer on the metal layer, the exposed sides of the dielectric layer are covered with a polymer diffusion barrier.
    Type: Application
    Filed: May 7, 2008
    Publication date: September 4, 2008
    Inventors: Robert B. Turkot, Justin K. Brask, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Uday Shah, Suman Datta, Robert S. Chau