Patents by Inventor Mark L. Doczy

Mark L. Doczy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PERPENDICULAR SPIN TRANSFER TORQUE MEMORY (STTM) DEVICE WITH ENHANCED STABILITY AND METHOD TO FORM SAME
    Publication number: 20140175575
    Abstract: Perpendicular spin transfer torque memory (STTM) devices with enhanced stability and methods of fabricating perpendicular STTM devices with enhanced stability are described. For example, a material layer stack for a magnetic tunneling junction includes a fixed magnetic layer. A dielectric layer is disposed above the fixed magnetic layer. A free magnetic layer is disposed above the dielectric layer. A conductive oxide material layer is disposed on the free magnetic layer.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Inventors: Brian S. Doyle, Charles C. Kuo, Kaan Oguz, Uday Shah, Elijah V. Karpov, Roksana Golizadeh Mojarad, Mark L. Doczy, Robert S. Chau
  • PERPENDICULAR SPIN TRANSFER TORQUE MEMORY (STTM) DEVICE HAVING OFFSET CELLS AND METHOD TO FORM SAME
    Publication number: 20140175583
    Abstract: Perpendicular spin transfer torque memory (STTM) devices having offset cells and methods of fabricating perpendicular STTM devices having offset cells are described. For example, a spin torque transfer memory (STTM) array includes a first load line disposed above a substrate and having only a first STTM device. The STTM array also includes a second load line disposed above the substrate, adjacent the first load line, and having only a second STTM device, the second STTM device non-co-planar with the first STTM device.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Inventors: Brian S. Doyle, David L. Kencke, Charles C. Kuo, Uday Shah, Kaan Oguz, Mark L. Doczy, Satyarth Suri, Clair Webb
  • FIELD EFFECT TRANSISTOR WITH NARROW BANDGAP SOURCE AND DRAIN REGIONS AND METHOD OF FABRICATION
    Publication number: 20140103456
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Application
    Filed: December 20, 2013
    Publication date: April 17, 2014
    Inventors: Robert S. Chau, Suman Datta, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz
  • GATE ELECTRODE HAVING A CAPPING LAYER
    Publication number: 20140103458
    Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.
    Type: Application
    Filed: December 20, 2013
    Publication date: April 17, 2014
    Inventors: Gilbert Dewey, Mark L. Doczy, Suman Datta, Justin K. Brask, Matthew V. Metz
  • DECREASED SWITCHING CURRENT IN SPIN-TRANSFER TORQUE MEMORY
    Publication number: 20140092677
    Abstract: Switching current in Spin-Transfer Torque Memory (STTM) can be decreased. A magnetic memory cell is driven with a first pulse on a write line of the memory cell to heat the cell. The cell is then driven with a second pulse on the write line to set the state of the cell.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: Elijah V. Karpov, Brian S. Doyle, Kaan Oguz, Satyarth Suri, Robert S. Chau, Charles C. Kuo, Mark L. Doczy
  • PERPENDICULAR MTJ STACKS WITH MAGNETIC ANISOTROPY ENHANCING LAYER AND CRYSTALLIZATION BARRIER LAYER
    Publication number: 20140084398
    Abstract: Magnetic tunnel junctions (MTJ) suitable for spin transfer torque memory (STTM) devices, include perpendicular magnetic layers and one or more anisotropy enhancing layer(s) separated from a free magnetic layer by a crystallization barrier layer. In embodiments, an anisotropy enhancing layer improves perpendicular orientation of the free magnetic layer while the crystallization barrier improves tunnel magnetoresistance (TMR) ratio with better alignment of crystalline texture of the free magnetic layer with that of a tunneling layer.
    Type: Application
    Filed: September 26, 2012
    Publication date: March 27, 2014
    Inventors: Kaan OGUZ, Mark L. DOCZY, Brian DOYLE, Uday SHAH, David L. KENCKE, Roksana GOLIZADEH MOJARAD, Robert S. CHAU
  • SPIN TRANSFER TORQUE MEMORY (STTM) DEVICE WITH TOPOGRAPHICALLY SMOOTH ELECTRODE AND METHOD TO FORM SAME
    Publication number: 20140084399
    Abstract: Spin transfer torque memory (STTM) devices with topographically smooth electrodes and methods of fabricating STTM devices with topographically smooth electrodes are described. For example, a material layer stack for a magnetic tunneling junction includes a topographically smooth bottom electrode, a topographically smooth dielectric layer disposed above the bottom electrode, and a free magnetic layer disposed above the topographically smooth dielectric layer.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Inventors: Mark L. Doczy, Kaan Oguz, Brian S. Doyle, Robert S. Chau
  • Field effect transistor with narrow bandgap source and drain regions and method of fabrication
    Patent number: 8664694
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: March 4, 2014
    Assignee: Intel Corporation
    Inventors: Robert S. Chau, Suman Datta, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz
  • EXTREME HIGH MOBILITY CMOS LOGIC
    Publication number: 20130328015
    Abstract: A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.
    Type: Application
    Filed: August 8, 2013
    Publication date: December 12, 2013
    Inventors: Suman Datta, Mantu K. Hudait, Mark L. Doczy, Jack T. Kavalieros, Majumdar Amian, Justin K. Brask, Been-Yih Jin, Matthew V. Metz, Robert S. Chau
  • Extreme high mobility CMOS logic
    Patent number: 8518768
    Abstract: A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: August 27, 2013
    Assignee: Intel Corporation
    Inventors: Suman Datta, Mantu K. Hudait, Mark L. Doczy, Jack T. Kavalieros, Majumdar Amian, Justin K. Brask, Been-Yih Jin, Matthew V. Metz, Robert S. Chau
  • GATE ELECTRODE HAVING A CAPPING LAYER
    Publication number: 20130161766
    Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.
    Type: Application
    Filed: February 19, 2013
    Publication date: June 27, 2013
    Inventors: Gilbert Dewey, Mark L. Doczy, Suman Datta, Justin K. Brask, Matthew V. Metz
  • FIELD EFFECT TRANSISTOR WITH NARROW BANDGAP SOURCE AND DRAIN REGIONS AND METHOD OF FABRICATION
    Publication number: 20130146945
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Application
    Filed: January 28, 2013
    Publication date: June 13, 2013
    Inventors: Robert S. Chau, Suman Datta, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz
  • Gate electrode having a capping layer
    Patent number: 8390082
    Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: March 5, 2013
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Mark L. Doczy, Suman Datta, Justin K. Brask, Matthew V. Metz
  • Field effect transistor with narrow bandgap source and drain regions and method of fabrication
    Patent number: 8368135
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: February 5, 2013
    Assignee: Intel Corporation
    Inventors: Robert S. Chau, Suman Datta, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz
  • FIELD EFFECT TRANSISTOR WITH NARROW BANDGAP SOURCE AND DRAIN REGIONS AND METHOD OF FABRICATION
    Publication number: 20120205729
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Application
    Filed: April 23, 2012
    Publication date: August 16, 2012
    Inventors: Robert S. Chau, Suman Datta, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz
  • EXTREME HIGH MOBILITY CMOS LOGIC
    Publication number: 20120199813
    Abstract: A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.
    Type: Application
    Filed: April 18, 2012
    Publication date: August 9, 2012
    Applicant: Intel Corporation
    Inventors: Suman Datta, Mantu K. Hudait, Mark L. Doczy, Jack T. Kavalieros, Majumdar Amian, Justin K. Brask, Been-Yih Jin, Matthew V. Metz, Robert S. Chau
  • Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
    Patent number: 8193567
    Abstract: A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: June 5, 2012
    Assignee: Intel Corporation
    Inventors: Jack T. Kavalieros, Justin K. Brask, Brian S. Doyle, Uday Shah, Suman Datta, Mark L. Doczy, Matthew V. Metz, Robert S. Chau
  • Field effect transistor with narrow bandgap source and drain regions and method of fabrication
    Patent number: 8183646
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Grant
    Filed: February 4, 2011
    Date of Patent: May 22, 2012
    Assignee: Intel Corporation
    Inventors: Robert S. Chau, Suman Datta, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz
  • Extreme high mobility CMOS logic
    Patent number: 8183556
    Abstract: A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: May 22, 2012
    Assignee: Intel Corporation
    Inventors: Suman Datt{dot over (a)}, Mantu K. Hudait, Mark L. Doczy, Jack T. Kavalieros, Majumdar Amlan, Justin K. Brask, Been-Yih Jin, Matthew V. Metz, Robert S. Chau
  • Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate
    Patent number: 8148786
    Abstract: A complementary metal oxide semiconductor integrated circuit may be formed with a PMOS device formed using a replacement metal gate and a raised source drain. The raised source drain may be formed of epitaxially deposited silicon germanium material that is doped p-type. The replacement metal gate process results in a metal gate electrode and may involve the removal of a nitride etch stop layer.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: April 3, 2012
    Assignee: Intel Corporation
    Inventors: Jack Kavalieros, Annalisa Cappellani, Justin K. Brask, Mark L. Doczy, Matthew V. Metz, Suman Datta, Chris E. Barns, Robert S. Chau