Patents by Inventor Mark L. Doczy

Mark L. Doczy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Inducing strain in the channels of metal gate transistors
    Patent number: 8129795
    Abstract: In a metal gate replacement process, strain may be selectively induced in the channels of NMOS and PMOS transistors. For example, a material having a higher coefficient of thermal expansion than the substrate may be used to form the gate electrodes of PMOS transistors. A material with a lower coefficient of thermal expansion than that of the substrate may be used to form the gate electrodes of NMOS transistors.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: March 6, 2012
    Assignee: Intel Corporation
    Inventors: Suman Datta, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Justin K. Brask, Robert S. Chau, Brian S. Doyle
  • Forming integrated circuits with replacement metal gate electrodes
    Patent number: 8119508
    Abstract: In a metal gate replacement process, a stack of at least two polysilicon layers or other materials may be formed. Sidewall spacers may be formed on the stack. The stack may then be planarized. Next, the upper layer of the stack may be selectively removed. Then, the exposed portions of the sidewall spacers may be selectively removed. Finally, the lower portion of the stack may be removed to form a T-shaped trench which may be filled with the metal replacement.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: February 21, 2012
    Assignee: Intel Corporation
    Inventors: Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew V. Metz, Suman Datta, Uday Shah, Robert S. Chau
  • Methods for fabricating PMOS metal gate structures
    Patent number: 8021940
    Abstract: Methods of forming a microelectronic structure are described. Those methods may include forming a gate dielectric layer on a substrate, forming a metal gate layer on the gate dielectric layer, and then forming a polysilicon layer on the metal gate layer in situ, wherein the metal gate layer is not exposed to air.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: September 20, 2011
    Assignee: Intel Corporation
    Inventors: Matthew V. Metz, Mark L. Doczy, Gilbert Dewey, Jack Kavalieros
  • Dielectric interface for group III-V semiconductor device
    Patent number: 7989280
    Abstract: A Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: August 2, 2011
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Suman Datta, Mark L. Doczy, James M. Blackwell, Matthew V. Metz, Jack T. Kavalieros, Robert S. Chau
  • GATE ELECTRODE HAVING A CAPPING LAYER
    Publication number: 20110156174
    Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.
    Type: Application
    Filed: March 9, 2011
    Publication date: June 30, 2011
    Inventors: Gilbert Dewey, Mark L. Doczy, Suman Datta, Justin K. Brask, Matthew V. Metz
  • Forming abrupt source drain metal gate transistors
    Patent number: 7951673
    Abstract: A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: May 31, 2011
    Assignee: Intel Corporation
    Inventors: Nick Lindert, Suman Datta, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Justin K. Brask, Robert S. Chau, Mark Bohr, Anand S. Murthy
  • FIELD EFFECT TRANSISTOR WITH NARROW BANDGAP SOURCE AND DRAIN REGIONS AND METHOD OF FABRICATION
    Publication number: 20110121393
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Application
    Filed: February 4, 2011
    Publication date: May 26, 2011
    Inventors: Robert S. Chau, Suman Datta, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz
  • Inducing Strain in the Channels of Metal Gate Transistors
    Publication number: 20110115028
    Abstract: In a metal gate replacement process, strain may be selectively induced in the channels of NMOS and PMOS transistors. For example, a material having a higher coefficient of thermal expansion than the substrate may be used to form the gate electrodes of PMOS transistors. A material with a lower coefficient of thermal expansion than that of the substrate may be used to form the gate electrodes of NMOS transistors.
    Type: Application
    Filed: January 26, 2011
    Publication date: May 19, 2011
    Inventors: Suman Datta, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Justin K. Brask, Robert S. Chau, Brian S. Doyle
  • Gate electrode having a capping layer
    Patent number: 7915694
    Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: March 29, 2011
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Mark L. Doczy, Suman Datta, Justin K. Brask, Matthew V. Metz
  • METHOD FOR FABRICATING TRANSISTOR WITH THINNED CHANNEL
    Publication number: 20110062520
    Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
    Type: Application
    Filed: November 18, 2010
    Publication date: March 17, 2011
    Inventors: Justin K. Brask, Robert S. Chau, Suman Datta, Mark L. Doczy, Brian S. Doyle, Jack T. Kavalieros, Amlan Majumdar, Matthew V. Metz, Marko Radosavljevic
  • Inducing strain in the channels of metal gate transistors
    Patent number: 7902058
    Abstract: In a metal gate replacement process, strain may be selectively induced in the channels of NMOS and PMOS transistors. For example, a material having a higher coefficient of thermal expansion than the substrate may be used to form the gate electrodes of PMOS transistors. A material with a lower coefficient of thermal expansion than that of the substrate may be used to form the gate electrodes of NMOS transistors.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: March 8, 2011
    Assignee: Intel Corporation
    Inventors: Suman Datta, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Justin K. Brask, Robert S. Chau, Brian S. Doyle
  • Block contact architectures for nanoscale channel transistors
    Patent number: 7898041
    Abstract: A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: March 1, 2011
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Amlan Majumdar, Brian S. Doyle, Jack Kavalieros, Mark L. Doczy, Justin K. Brask, Uday Shah, Suman Datta, Robert S. Chau
  • Field effect transistor with narrow bandgap source and drain regions and method of fabrication
    Patent number: 7893506
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: February 22, 2011
    Assignee: Intel Corporation
    Inventors: Robert S. Chau, Suman Datta, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz
  • CMOS device with metal and silicide gate electrodes and a method for making it
    Patent number: 7883951
    Abstract: A semiconductor device and a method for forming it are described. The semiconductor device comprises a metal NMOS gate electrode that is formed on a first part of a substrate, and a silicide PMOS gate electrode that is formed on a second part of the substrate.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: February 8, 2011
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Mark L. Doczy, Jack Kavalieros, Matthew V. Metz, Chris E. Barns, Uday Shah, Suman Datta, Christopher D. Thomas, Robert S. Chau
  • Field effect transistor with metal source/drain regions
    Patent number: 7879675
    Abstract: A semiconductor device comprising a gate electrode formed on a gate dielectric layer formed on a semiconductor film. A pair of source/drain regions are formed adjacent the channel region on opposite sides of the gate electrode. The source and drain regions each comprise a semiconductor portion adjacent to and in contact with the semiconductor channel and a metal portion adjacent to and in contact with the semiconductor portion.
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: February 1, 2011
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Suman Datta, Brian S. Doyle, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Amian Majumdar, Robert S. Chau
  • Semiconductor device with a high-k gate dielectric and a metal gate electrode
    Patent number: 7875937
    Abstract: A semiconductor device is described. That semiconductor device comprises a high-k gate dielectric layer that is formed on a substrate that applies strain to the high-k gate dielectric layer, and a metal gate electrode that is formed on the high-k gate dielectric layer.
    Type: Grant
    Filed: October 7, 2008
    Date of Patent: January 25, 2011
    Assignee: Intel Corporation
    Inventors: Matthew V. Metz, Suman Datta, Mark L. Doczy, Justin K. Brask, Jack Kavalieros, Robert S. Chau
  • Method for fabricating transistor with thinned channel
    Patent number: 7858481
    Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: December 28, 2010
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Robert S. Chau, Suman Datta, Mark L. Doczy, Brian S. Doyle, Jack T. Kavalieros, Amlan Majumdar, Matthew V. Metz, Marko Radosavljevic
  • FIELD EFFECT TRANSISTOR WITH NARROW BANDGAP SOURCE AND DRAIN REGIONS AND METHOD OF FABRICATION
    Publication number: 20100295129
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Application
    Filed: August 4, 2010
    Publication date: November 25, 2010
    Inventors: Robert S. Chau, Suman Datta, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz
  • Field effect transistor with narrow bandgap source and drain regions and method of fabrication
    Patent number: 7825481
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: November 2, 2010
    Assignee: Intel Corporation
    Inventors: Robert S. Chau, Suman Datta, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz
  • FORMING INTEGRATED CIRCUITS WITH REPLACEMENT METAL GATE ELECTRODES
    Publication number: 20100219456
    Abstract: In a metal gate replacement process, a stack of at least two polysilicon layers or other materials may be formed. Sidewall spacers may be formed on the stack. The stack may then be planarized. Next, the upper layer of the stack may be selectively removed. Then, the exposed portions of the sidewall spacers may be selectively removed. Finally, the lower portion of the stack may be removed to form a T-shaped trench which may be filled with the metal replacement.
    Type: Application
    Filed: May 17, 2010
    Publication date: September 2, 2010
    Inventors: Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew V. Metz, Suman Datta, Uday Shah, Robert S. Chau